^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* Copyright (c) 2015 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Permission to use, copy, modify, and/or distribute this software for any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * purpose with or without fee is hereby granted, provided that the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copyright notice and this permission notice appear in all copies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __QCOM_CLK_IPQ4019_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __QCOM_CLK_IPQ4019_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GCC_DUMMY_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AUDIO_CLK_SRC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BLSP1_QUP1_I2C_APPS_CLK_SRC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BLSP1_QUP1_SPI_APPS_CLK_SRC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BLSP1_QUP2_I2C_APPS_CLK_SRC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BLSP1_QUP2_SPI_APPS_CLK_SRC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BLSP1_UART1_APPS_CLK_SRC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BLSP1_UART2_APPS_CLK_SRC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GCC_USB3_MOCK_UTMI_CLK_SRC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GCC_APPS_CLK_SRC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GCC_APPS_AHB_CLK_SRC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GP1_CLK_SRC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GP2_CLK_SRC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GP3_CLK_SRC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SDCC1_APPS_CLK_SRC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FEPHY_125M_DLY_CLK_SRC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WCSS2G_CLK_SRC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WCSS5G_CLK_SRC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GCC_APSS_AHB_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GCC_AUDIO_AHB_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GCC_AUDIO_PWM_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GCC_BLSP1_AHB_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GCC_BLSP1_QUP1_I2C_APPS_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GCC_BLSP1_QUP1_SPI_APPS_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GCC_BLSP1_QUP2_I2C_APPS_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GCC_BLSP1_QUP2_SPI_APPS_CLK 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GCC_BLSP1_UART1_APPS_CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GCC_BLSP1_UART2_APPS_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GCC_DCD_XO_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GCC_GP1_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GCC_GP2_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GCC_GP3_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GCC_BOOT_ROM_AHB_CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GCC_CRYPTO_AHB_CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GCC_CRYPTO_AXI_CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GCC_CRYPTO_CLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GCC_ESS_CLK 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GCC_IMEM_AXI_CLK 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GCC_IMEM_CFG_AHB_CLK 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GCC_PCIE_AHB_CLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GCC_PCIE_AXI_M_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GCC_PCIE_AXI_S_CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GCC_PCNOC_AHB_CLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GCC_PRNG_AHB_CLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GCC_QPIC_AHB_CLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GCC_QPIC_CLK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GCC_SDCC1_AHB_CLK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GCC_SDCC1_APPS_CLK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GCC_SNOC_PCNOC_AHB_CLK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GCC_SYS_NOC_125M_CLK 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GCC_SYS_NOC_AXI_CLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GCC_TCSR_AHB_CLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GCC_TLMM_AHB_CLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GCC_USB2_MASTER_CLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GCC_USB2_SLEEP_CLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GCC_USB2_MOCK_UTMI_CLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GCC_USB3_MASTER_CLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GCC_USB3_SLEEP_CLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GCC_USB3_MOCK_UTMI_CLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GCC_WCSS2G_CLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GCC_WCSS2G_REF_CLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GCC_WCSS2G_RTC_CLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GCC_WCSS5G_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GCC_WCSS5G_REF_CLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GCC_WCSS5G_RTC_CLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GCC_APSS_DDRPLL_VCO 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GCC_SDCC_PLLDIV_CLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GCC_FEPLL_VCO 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GCC_FEPLL125_CLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GCC_FEPLL125DLY_CLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GCC_FEPLL200_CLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GCC_FEPLL500_CLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GCC_FEPLL_WCSS2G_CLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GCC_FEPLL_WCSS5G_CLK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GCC_APSS_CPU_PLLDIV_CLK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GCC_PCNOC_AHB_CLK_SRC 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define WIFI0_CPU_INIT_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define WIFI0_RADIO_SRIF_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define WIFI0_RADIO_WARM_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define WIFI0_RADIO_COLD_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WIFI0_CORE_WARM_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WIFI0_CORE_COLD_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WIFI1_CPU_INIT_RESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WIFI1_RADIO_SRIF_RESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WIFI1_RADIO_WARM_RESET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WIFI1_RADIO_COLD_RESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WIFI1_CORE_WARM_RESET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WIFI1_CORE_COLD_RESET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define USB3_UNIPHY_PHY_ARES 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define USB3_HSPHY_POR_ARES 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define USB3_HSPHY_S_ARES 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define USB2_HSPHY_POR_ARES 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define USB2_HSPHY_S_ARES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCIE_PHY_AHB_ARES 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCIE_AHB_ARES 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCIE_PWR_ARES 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCIE_PIPE_STICKY_ARES 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCIE_AXI_M_STICKY_ARES 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCIE_PHY_ARES 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCIE_PARF_XPU_ARES 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCIE_AXI_S_XPU_ARES 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCIE_AXI_M_VMIDMT_ARES 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCIE_PIPE_ARES 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCIE_AXI_S_ARES 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCIE_AXI_M_ARES 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ESS_RESET 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_BLSP1_BCR 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_BLSP1_QUP1_BCR 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_BLSP1_UART1_BCR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_BLSP1_QUP2_BCR 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_BLSP1_UART2_BCR 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GCC_BIMC_BCR 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GCC_TLMM_BCR 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GCC_IMEM_BCR 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GCC_ESS_BCR 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_PRNG_BCR 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_BOOT_ROM_BCR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_CRYPTO_BCR 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_SDCC1_BCR 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_SEC_CTRL_BCR 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_AUDIO_BCR 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GCC_QPIC_BCR 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GCC_PCIE_BCR 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GCC_USB2_BCR 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GCC_USB2_PHY_BCR 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GCC_USB3_BCR 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_USB3_PHY_BCR 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GCC_SYSTEM_NOC_BCR 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_PCNOC_BCR 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_DCD_BCR 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCC_SNOC_BUS_TIMEOUT0_BCR 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCC_SNOC_BUS_TIMEOUT1_BCR 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCC_SNOC_BUS_TIMEOUT2_BCR 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GCC_SNOC_BUS_TIMEOUT3_BCR 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GCC_TCSR_BCR 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GCC_QDSS_BCR 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GCC_MPM_BCR 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GCC_SPDM_BCR 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags