Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_CLK_APQ_GCC_8084_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define GPLL0						0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define GPLL0_VOTE					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define GPLL1						2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define GPLL1_VOTE					3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define GPLL2						4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define GPLL2_VOTE					5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define GPLL3						6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define GPLL3_VOTE					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define GPLL4						8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define GPLL4_VOTE					9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CONFIG_NOC_CLK_SRC				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PERIPH_NOC_CLK_SRC				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SYSTEM_NOC_CLK_SRC				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define BLSP_UART_SIM_CLK_SRC				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define QDSS_TSCTR_CLK_SRC				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define UFS_AXI_CLK_SRC					15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define RPM_CLK_SRC					16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define KPSS_AHB_CLK_SRC				17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define QDSS_AT_CLK_SRC					18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define BIMC_DDR_CLK_SRC				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define USB30_MASTER_CLK_SRC				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define USB30_SEC_MASTER_CLK_SRC			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define USB_HSIC_AHB_CLK_SRC				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MMSS_BIMC_GFX_CLK_SRC				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define QDSS_STM_CLK_SRC				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ACC_CLK_SRC					25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SEC_CTRL_CLK_SRC				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define BLSP1_QUP1_I2C_APPS_CLK_SRC			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define BLSP1_QUP1_SPI_APPS_CLK_SRC			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define BLSP1_QUP2_I2C_APPS_CLK_SRC			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define BLSP1_QUP2_SPI_APPS_CLK_SRC			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define BLSP1_QUP3_I2C_APPS_CLK_SRC			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define BLSP1_QUP3_SPI_APPS_CLK_SRC			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define BLSP1_QUP4_I2C_APPS_CLK_SRC			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define BLSP1_QUP4_SPI_APPS_CLK_SRC			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define BLSP1_QUP5_I2C_APPS_CLK_SRC			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define BLSP1_QUP5_SPI_APPS_CLK_SRC			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define BLSP1_QUP6_I2C_APPS_CLK_SRC			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define BLSP1_QUP6_SPI_APPS_CLK_SRC			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define BLSP1_UART1_APPS_CLK_SRC			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define BLSP1_UART2_APPS_CLK_SRC			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define BLSP1_UART3_APPS_CLK_SRC			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define BLSP1_UART4_APPS_CLK_SRC			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define BLSP1_UART5_APPS_CLK_SRC			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define BLSP1_UART6_APPS_CLK_SRC			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define BLSP2_QUP1_I2C_APPS_CLK_SRC			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define BLSP2_QUP1_SPI_APPS_CLK_SRC			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define BLSP2_QUP2_I2C_APPS_CLK_SRC			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define BLSP2_QUP2_SPI_APPS_CLK_SRC			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define BLSP2_QUP3_I2C_APPS_CLK_SRC			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define BLSP2_QUP3_SPI_APPS_CLK_SRC			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define BLSP2_QUP4_I2C_APPS_CLK_SRC			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define BLSP2_QUP4_SPI_APPS_CLK_SRC			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define BLSP2_QUP5_I2C_APPS_CLK_SRC			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define BLSP2_QUP5_SPI_APPS_CLK_SRC			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define BLSP2_QUP6_I2C_APPS_CLK_SRC			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define BLSP2_QUP6_SPI_APPS_CLK_SRC			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define BLSP2_UART1_APPS_CLK_SRC			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define BLSP2_UART2_APPS_CLK_SRC			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define BLSP2_UART3_APPS_CLK_SRC			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define BLSP2_UART4_APPS_CLK_SRC			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define BLSP2_UART5_APPS_CLK_SRC			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define BLSP2_UART6_APPS_CLK_SRC			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CE1_CLK_SRC					63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CE2_CLK_SRC					64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CE3_CLK_SRC					65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define GP1_CLK_SRC					66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define GP2_CLK_SRC					67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define GP3_CLK_SRC					68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PDM2_CLK_SRC					69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define QDSS_TRACECLKIN_CLK_SRC				70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define RBCPR_CLK_SRC					71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SATA_ASIC0_CLK_SRC				72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SATA_PMALIVE_CLK_SRC				73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SATA_RX_CLK_SRC					74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SATA_RX_OOB_CLK_SRC				75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SDCC1_APPS_CLK_SRC				76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SDCC2_APPS_CLK_SRC				77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SDCC3_APPS_CLK_SRC				78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SDCC4_APPS_CLK_SRC				79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SPMI_AHB_CLK_SRC				81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SPMI_SER_CLK_SRC				82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TSIF_REF_CLK_SRC				83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define USB30_MOCK_UTMI_CLK_SRC				84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define USB30_SEC_MOCK_UTMI_CLK_SRC			85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define USB_HS_SYSTEM_CLK_SRC				86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define USB_HSIC_CLK_SRC				87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define USB_HSIC_IO_CAL_CLK_SRC				88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define USB_HSIC_MOCK_UTMI_CLK_SRC			89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define USB_HSIC_SYSTEM_CLK_SRC				90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GCC_BAM_DMA_AHB_CLK				91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DDR_CLK_SRC					93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GCC_BIMC_CFG_AHB_CLK				94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GCC_BIMC_CLK					95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GCC_BIMC_KPSS_AXI_CLK				96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCC_BIMC_SLEEP_CLK				97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GCC_BIMC_SYSNOC_AXI_CLK				98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GCC_BIMC_XO_CLK					99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GCC_BLSP1_AHB_CLK				100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GCC_BLSP1_SLEEP_CLK				101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GCC_BLSP1_QUP1_I2C_APPS_CLK			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GCC_BLSP1_QUP1_SPI_APPS_CLK			103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GCC_BLSP1_QUP2_I2C_APPS_CLK			104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GCC_BLSP1_QUP2_SPI_APPS_CLK			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GCC_BLSP1_QUP3_I2C_APPS_CLK			106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GCC_BLSP1_QUP3_SPI_APPS_CLK			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GCC_BLSP1_QUP4_I2C_APPS_CLK			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GCC_BLSP1_QUP4_SPI_APPS_CLK			109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GCC_BLSP1_QUP5_I2C_APPS_CLK			110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GCC_BLSP1_QUP5_SPI_APPS_CLK			111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GCC_BLSP1_QUP6_I2C_APPS_CLK			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GCC_BLSP1_QUP6_SPI_APPS_CLK			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GCC_BLSP1_UART1_APPS_CLK			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GCC_BLSP1_UART1_SIM_CLK				115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GCC_BLSP1_UART2_APPS_CLK			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_BLSP1_UART2_SIM_CLK				117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_BLSP1_UART3_APPS_CLK			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_BLSP1_UART3_SIM_CLK				119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_BLSP1_UART4_APPS_CLK			120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_BLSP1_UART4_SIM_CLK				121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GCC_BLSP1_UART5_APPS_CLK			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GCC_BLSP1_UART5_SIM_CLK				123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GCC_BLSP1_UART6_APPS_CLK			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GCC_BLSP1_UART6_SIM_CLK				125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_BLSP2_AHB_CLK				126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_BLSP2_SLEEP_CLK				127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_BLSP2_QUP1_I2C_APPS_CLK			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_BLSP2_QUP1_SPI_APPS_CLK			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_BLSP2_QUP2_I2C_APPS_CLK			130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_BLSP2_QUP2_SPI_APPS_CLK			131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GCC_BLSP2_QUP3_I2C_APPS_CLK			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GCC_BLSP2_QUP3_SPI_APPS_CLK			133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GCC_BLSP2_QUP4_I2C_APPS_CLK			134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GCC_BLSP2_QUP4_SPI_APPS_CLK			135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GCC_BLSP2_QUP5_I2C_APPS_CLK			136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_BLSP2_QUP5_SPI_APPS_CLK			137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GCC_BLSP2_QUP6_I2C_APPS_CLK			138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_BLSP2_QUP6_SPI_APPS_CLK			139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_BLSP2_UART1_APPS_CLK			140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCC_BLSP2_UART1_SIM_CLK				141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCC_BLSP2_UART2_APPS_CLK			142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCC_BLSP2_UART2_SIM_CLK				143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GCC_BLSP2_UART3_APPS_CLK			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GCC_BLSP2_UART3_SIM_CLK				145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GCC_BLSP2_UART4_APPS_CLK			146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GCC_BLSP2_UART4_SIM_CLK				147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GCC_BLSP2_UART5_APPS_CLK			148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GCC_BLSP2_UART5_SIM_CLK				149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GCC_BLSP2_UART6_APPS_CLK			150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GCC_BLSP2_UART6_SIM_CLK				151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GCC_BOOT_ROM_AHB_CLK				152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GCC_CE1_AHB_CLK					153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GCC_CE1_AXI_CLK					154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GCC_CE1_CLK					155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GCC_CE2_AHB_CLK					156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GCC_CE2_AXI_CLK					157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GCC_CE2_CLK					158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GCC_CE3_AHB_CLK					159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GCC_CE3_AXI_CLK					160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GCC_CE3_CLK					161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK			162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK			163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK			164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK			165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK			166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK			167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK			168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK			169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GCC_CFG_NOC_AHB_CLK				170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GCC_CFG_NOC_DDR_CFG_CLK				171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GCC_CFG_NOC_RPM_AHB_CLK				172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GCC_COPSS_SMMU_AHB_CLK				173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GCC_COPSS_SMMU_AXI_CLK				174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GCC_DCD_XO_CLK					175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GCC_BIMC_DDR_CH0_CLK				176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GCC_BIMC_DDR_CH1_CLK				177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GCC_BIMC_DDR_CPLL0_CLK				178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GCC_BIMC_DDR_CPLL1_CLK				179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GCC_BIMC_GFX_CLK				180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GCC_DDR_DIM_CFG_CLK				181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GCC_DDR_DIM_SLEEP_CLK				182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GCC_DEHR_CLK					183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GCC_AHB_CLK					184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GCC_IM_SLEEP_CLK				185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GCC_XO_CLK					186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GCC_XO_DIV4_CLK					187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GCC_GP1_CLK					188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GCC_GP2_CLK					189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GCC_GP3_CLK					190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GCC_IMEM_AXI_CLK				191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GCC_IMEM_CFG_AHB_CLK				192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GCC_KPSS_AHB_CLK				193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GCC_KPSS_AXI_CLK				194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GCC_LPASS_MPORT_AXI_CLK				195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GCC_LPASS_Q6_AXI_CLK				196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GCC_LPASS_SWAY_CLK				197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GCC_MMSS_BIMC_GFX_CLK				198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GCC_MMSS_NOC_AT_CLK				199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GCC_MMSS_NOC_CFG_AHB_CLK			200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK		201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define GCC_OCMEM_NOC_CFG_AHB_CLK			202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define GCC_OCMEM_SYS_NOC_AXI_CLK			203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GCC_MPM_AHB_CLK					204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GCC_MSG_RAM_AHB_CLK				205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GCC_NOC_CONF_XPU_AHB_CLK			206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GCC_PDM2_CLK					207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GCC_PDM_AHB_CLK					208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GCC_PDM_XO4_CLK					209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GCC_PERIPH_NOC_AHB_CLK				210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GCC_PERIPH_NOC_AT_CLK				211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GCC_PERIPH_NOC_CFG_AHB_CLK			212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK			213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK			214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GCC_PERIPH_XPU_AHB_CLK				215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK			216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK			217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK			218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK			219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK			220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define GCC_PRNG_AHB_CLK				221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GCC_QDSS_AT_CLK					222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define GCC_QDSS_CFG_AHB_CLK				223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GCC_QDSS_DAP_AHB_CLK				224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define GCC_QDSS_DAP_CLK				225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define GCC_QDSS_ETR_USB_CLK				226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GCC_QDSS_STM_CLK				227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GCC_QDSS_TRACECLKIN_CLK				228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GCC_QDSS_TSCTR_DIV16_CLK			229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define GCC_QDSS_TSCTR_DIV2_CLK				230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GCC_QDSS_TSCTR_DIV3_CLK				231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GCC_QDSS_TSCTR_DIV4_CLK				232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GCC_QDSS_TSCTR_DIV8_CLK				233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GCC_QDSS_RBCPR_XPU_AHB_CLK			234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GCC_RBCPR_AHB_CLK				235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GCC_RBCPR_CLK					236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define GCC_RPM_BUS_AHB_CLK				237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define GCC_RPM_PROC_HCLK				238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define GCC_RPM_SLEEP_CLK				239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define GCC_RPM_TIMER_CLK				240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define GCC_SATA_ASIC0_CLK				241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GCC_SATA_AXI_CLK				242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define GCC_SATA_CFG_AHB_CLK				243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define GCC_SATA_PMALIVE_CLK				244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define GCC_SATA_RX_CLK					245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define GCC_SATA_RX_OOB_CLK				246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define GCC_SDCC1_AHB_CLK				247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define GCC_SDCC1_APPS_CLK				248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GCC_SDCC1_CDCCAL_FF_CLK				249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define GCC_SDCC1_CDCCAL_SLEEP_CLK			250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define GCC_SDCC2_AHB_CLK				251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define GCC_SDCC2_APPS_CLK				252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GCC_SDCC2_INACTIVITY_TIMERS_CLK			253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define GCC_SDCC3_AHB_CLK				254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define GCC_SDCC3_APPS_CLK				255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define GCC_SDCC3_INACTIVITY_TIMERS_CLK			256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define GCC_SDCC4_AHB_CLK				257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GCC_SDCC4_APPS_CLK				258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define GCC_SDCC4_INACTIVITY_TIMERS_CLK			259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define GCC_SEC_CTRL_ACC_CLK				260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define GCC_SEC_CTRL_AHB_CLK				261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK			262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define GCC_SEC_CTRL_CLK				263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define GCC_SEC_CTRL_SENSE_CLK				264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK			265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK			266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define GCC_SPDM_BIMC_CY_CLK				267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GCC_SPDM_CFG_AHB_CLK				268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define GCC_SPDM_DEBUG_CY_CLK				269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define GCC_SPDM_FF_CLK					270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define GCC_SPDM_MSTR_AHB_CLK				271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define GCC_SPDM_PNOC_CY_CLK				272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define GCC_SPDM_RPM_CY_CLK				273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define GCC_SPDM_SNOC_CY_CLK				274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define GCC_SPMI_AHB_CLK				275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define GCC_SPMI_CNOC_AHB_CLK				276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define GCC_SPMI_SER_CLK				277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define GCC_SPSS_AHB_CLK				278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define GCC_SNOC_CNOC_AHB_CLK				279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define GCC_SNOC_PNOC_AHB_CLK				280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define GCC_SYS_NOC_AT_CLK				281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define GCC_SYS_NOC_AXI_CLK				282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define GCC_SYS_NOC_KPSS_AHB_CLK			283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define GCC_SYS_NOC_QDSS_STM_AXI_CLK			284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define GCC_SYS_NOC_UFS_AXI_CLK				285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define GCC_SYS_NOC_USB3_AXI_CLK			286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define GCC_SYS_NOC_USB3_SEC_AXI_CLK			287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define GCC_TCSR_AHB_CLK				288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define GCC_TLMM_AHB_CLK				289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define GCC_TLMM_CLK					290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define GCC_TSIF_AHB_CLK				291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define GCC_TSIF_INACTIVITY_TIMERS_CLK			292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GCC_TSIF_REF_CLK				293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define GCC_UFS_AHB_CLK					294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define GCC_UFS_AXI_CLK					295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define GCC_UFS_RX_CFG_CLK				296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define GCC_UFS_RX_SYMBOL_0_CLK				297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define GCC_UFS_RX_SYMBOL_1_CLK				298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define GCC_UFS_TX_CFG_CLK				299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define GCC_UFS_TX_SYMBOL_0_CLK				300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define GCC_UFS_TX_SYMBOL_1_CLK				301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define GCC_USB2A_PHY_SLEEP_CLK				302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define GCC_USB2B_PHY_SLEEP_CLK				303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define GCC_USB30_MASTER_CLK				304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define GCC_USB30_MOCK_UTMI_CLK				305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define GCC_USB30_SLEEP_CLK				306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define GCC_USB30_SEC_MASTER_CLK			307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define GCC_USB30_SEC_MOCK_UTMI_CLK			308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GCC_USB30_SEC_SLEEP_CLK				309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define GCC_USB_HS_AHB_CLK				310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define GCC_USB_HS_INACTIVITY_TIMERS_CLK		311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define GCC_USB_HS_SYSTEM_CLK				312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define GCC_USB_HSIC_AHB_CLK				313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define GCC_USB_HSIC_CLK				314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define GCC_USB_HSIC_IO_CAL_CLK				315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define GCC_USB_HSIC_IO_CAL_SLEEP_CLK			316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define GCC_USB_HSIC_MOCK_UTMI_CLK			317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define GCC_USB_HSIC_SYSTEM_CLK				318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define PCIE_0_AUX_CLK_SRC				319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PCIE_0_PIPE_CLK_SRC				320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PCIE_1_AUX_CLK_SRC				321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PCIE_1_PIPE_CLK_SRC				322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define GCC_PCIE_0_AUX_CLK				323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define GCC_PCIE_0_CFG_AHB_CLK				324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define GCC_PCIE_0_MSTR_AXI_CLK				325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define GCC_PCIE_0_PIPE_CLK				326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define GCC_PCIE_0_SLV_AXI_CLK				327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define GCC_PCIE_1_AUX_CLK				328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define GCC_PCIE_1_CFG_AHB_CLK				329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define GCC_PCIE_1_MSTR_AXI_CLK				330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define GCC_PCIE_1_PIPE_CLK				331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define GCC_PCIE_1_SLV_AXI_CLK				332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* gdscs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define USB_HS_HSIC_GDSC				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PCIE0_GDSC					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PCIE1_GDSC					2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define USB30_GDSC					3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif