Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* DISP_CC clock registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DISP_CC_MDSS_AHB_CLK					0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DISP_CC_MDSS_AXI_CLK					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DISP_CC_MDSS_BYTE0_CLK					2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DISP_CC_MDSS_BYTE0_CLK_SRC				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DISP_CC_MDSS_BYTE0_INTF_CLK				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DISP_CC_MDSS_BYTE1_CLK					5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DISP_CC_MDSS_BYTE1_CLK_SRC				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DISP_CC_MDSS_BYTE1_INTF_CLK				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DISP_CC_MDSS_ESC0_CLK					8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DISP_CC_MDSS_ESC0_CLK_SRC				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DISP_CC_MDSS_ESC1_CLK					10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DISP_CC_MDSS_ESC1_CLK_SRC				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DISP_CC_MDSS_MDP_CLK					12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DISP_CC_MDSS_MDP_CLK_SRC				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DISP_CC_MDSS_MDP_LUT_CLK				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DISP_CC_MDSS_PCLK0_CLK					15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DISP_CC_MDSS_PCLK0_CLK_SRC				16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DISP_CC_MDSS_PCLK1_CLK					17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DISP_CC_MDSS_PCLK1_CLK_SRC				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DISP_CC_MDSS_ROT_CLK					19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DISP_CC_MDSS_ROT_CLK_SRC				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DISP_CC_MDSS_RSCC_AHB_CLK				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DISP_CC_MDSS_RSCC_VSYNC_CLK				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DISP_CC_MDSS_VSYNC_CLK					23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DISP_CC_MDSS_VSYNC_CLK_SRC				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DISP_CC_PLL0						25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DISP_CC_MDSS_DP_AUX_CLK					28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DISP_CC_MDSS_DP_AUX_CLK_SRC				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DISP_CC_MDSS_DP_CRYPTO_CLK				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DISP_CC_MDSS_DP_LINK_CLK				32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DISP_CC_MDSS_DP_LINK_CLK_SRC				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DISP_CC_MDSS_DP_LINK_INTF_CLK				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DISP_CC_MDSS_DP_PIXEL1_CLK				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DISP_CC_MDSS_DP_PIXEL_CLK				37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* DISP_CC Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DISP_CC_MDSS_RSCC_BCR					0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* DISP_CC GDSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MDSS_GDSC						0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif