^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DISP_CC_PLL0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DISP_CC_PLL0_OUT_EVEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DISP_CC_MDSS_AHB_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DISP_CC_MDSS_AHB_CLK_SRC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DISP_CC_MDSS_BYTE0_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DISP_CC_MDSS_BYTE0_CLK_SRC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DISP_CC_MDSS_BYTE0_INTF_CLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DISP_CC_MDSS_DP_AUX_CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DISP_CC_MDSS_DP_AUX_CLK_SRC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DISP_CC_MDSS_DP_CRYPTO_CLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DISP_CC_MDSS_DP_LINK_CLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DISP_CC_MDSS_DP_LINK_CLK_SRC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DISP_CC_MDSS_DP_LINK_INTF_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DISP_CC_MDSS_DP_PIXEL_CLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DISP_CC_MDSS_ESC0_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DISP_CC_MDSS_ESC0_CLK_SRC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DISP_CC_MDSS_MDP_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DISP_CC_MDSS_MDP_CLK_SRC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DISP_CC_MDSS_MDP_LUT_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DISP_CC_MDSS_PCLK0_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DISP_CC_MDSS_PCLK0_CLK_SRC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DISP_CC_MDSS_ROT_CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DISP_CC_MDSS_ROT_CLK_SRC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DISP_CC_MDSS_RSCC_AHB_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DISP_CC_MDSS_RSCC_VSYNC_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DISP_CC_MDSS_VSYNC_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DISP_CC_MDSS_VSYNC_CLK_SRC 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DISP_CC_XO_CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* DISP_CC GDSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MDSS_GDSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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