^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* CAM_CC clock registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CAM_CC_BPS_AHB_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CAM_CC_BPS_AREG_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CAM_CC_BPS_AXI_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CAM_CC_BPS_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CAM_CC_BPS_CLK_SRC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CAM_CC_CAMNOC_ATB_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CAM_CC_CAMNOC_AXI_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CAM_CC_CCI_CLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CAM_CC_CCI_CLK_SRC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CAM_CC_CPAS_AHB_CLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CAM_CC_CPHY_RX_CLK_SRC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CAM_CC_CSI0PHYTIMER_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CAM_CC_CSI0PHYTIMER_CLK_SRC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CAM_CC_CSI1PHYTIMER_CLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CAM_CC_CSI1PHYTIMER_CLK_SRC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CAM_CC_CSI2PHYTIMER_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CAM_CC_CSI2PHYTIMER_CLK_SRC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CAM_CC_CSI3PHYTIMER_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CAM_CC_CSI3PHYTIMER_CLK_SRC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CAM_CC_CSIPHY0_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CAM_CC_CSIPHY1_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CAM_CC_CSIPHY2_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CAM_CC_CSIPHY3_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CAM_CC_FAST_AHB_CLK_SRC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CAM_CC_FD_CORE_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CAM_CC_FD_CORE_CLK_SRC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CAM_CC_FD_CORE_UAR_CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CAM_CC_ICP_APB_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CAM_CC_ICP_ATB_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CAM_CC_ICP_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CAM_CC_ICP_CLK_SRC 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CAM_CC_ICP_CTI_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CAM_CC_ICP_TS_CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CAM_CC_IFE_0_AXI_CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CAM_CC_IFE_0_CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CAM_CC_IFE_0_CLK_SRC 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CAM_CC_IFE_0_CPHY_RX_CLK 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CAM_CC_IFE_0_CSID_CLK 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CAM_CC_IFE_0_CSID_CLK_SRC 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CAM_CC_IFE_0_DSP_CLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CAM_CC_IFE_1_AXI_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CAM_CC_IFE_1_CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CAM_CC_IFE_1_CLK_SRC 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CAM_CC_IFE_1_CPHY_RX_CLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CAM_CC_IFE_1_CSID_CLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CAM_CC_IFE_1_CSID_CLK_SRC 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CAM_CC_IFE_1_DSP_CLK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CAM_CC_IFE_LITE_CLK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CAM_CC_IFE_LITE_CLK_SRC 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CAM_CC_IFE_LITE_CPHY_RX_CLK 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CAM_CC_IFE_LITE_CSID_CLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CAM_CC_IFE_LITE_CSID_CLK_SRC 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CAM_CC_IPE_0_AHB_CLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CAM_CC_IPE_0_AREG_CLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CAM_CC_IPE_0_AXI_CLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CAM_CC_IPE_0_CLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CAM_CC_IPE_0_CLK_SRC 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CAM_CC_IPE_1_AHB_CLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CAM_CC_IPE_1_AREG_CLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CAM_CC_IPE_1_AXI_CLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CAM_CC_IPE_1_CLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CAM_CC_IPE_1_CLK_SRC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CAM_CC_JPEG_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CAM_CC_JPEG_CLK_SRC 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CAM_CC_LRME_CLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CAM_CC_LRME_CLK_SRC 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CAM_CC_MCLK0_CLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CAM_CC_MCLK0_CLK_SRC 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CAM_CC_MCLK1_CLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CAM_CC_MCLK1_CLK_SRC 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CAM_CC_MCLK2_CLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CAM_CC_MCLK2_CLK_SRC 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CAM_CC_MCLK3_CLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CAM_CC_MCLK3_CLK_SRC 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CAM_CC_PLL0 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CAM_CC_PLL0_OUT_EVEN 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CAM_CC_PLL1 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CAM_CC_PLL1_OUT_EVEN 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CAM_CC_PLL2 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CAM_CC_PLL2_OUT_EVEN 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CAM_CC_PLL3 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CAM_CC_PLL3_OUT_EVEN 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CAM_CC_SLOW_AHB_CLK_SRC 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CAM_CC_SOC_AHB_CLK 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CAM_CC_SYS_TMR_CLK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* CAM_CC Resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TITAN_CAM_CC_CCI_BCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TITAN_CAM_CC_CPAS_BCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TITAN_CAM_CC_CSI0PHY_BCR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TITAN_CAM_CC_CSI1PHY_BCR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TITAN_CAM_CC_CSI2PHY_BCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TITAN_CAM_CC_MCLK0_BCR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TITAN_CAM_CC_MCLK1_BCR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TITAN_CAM_CC_MCLK2_BCR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TITAN_CAM_CC_MCLK3_BCR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TITAN_CAM_CC_TITAN_TOP_BCR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* CAM_CC GDSCRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BPS_GDSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IPE_0_GDSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IPE_1_GDSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IFE_0_GDSC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IFE_1_GDSC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TITAN_TOP_GDSC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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