Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2014 Robert Jarzmik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __DT_BINDINGS_CLOCK_PXA2XX_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CLK_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLK_1WIRE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_AC97 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_AC97CONF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_ASSP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_BOOT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_BTUART 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_CAMERA 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_CIR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_CORE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_DMC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_FFUART 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_FICP 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_GPIO 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_HSIO2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_HWUART 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_I2C 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_I2S 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_IM 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_INC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_ISC 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_KEYPAD 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_LCD 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_MEMC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_MEMSTK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_MINI_IM 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_MINI_LCD 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_MMC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_MMC1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_MMC2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_MMC3 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_MSL 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_MSL0 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_MVED 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_NAND 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_NSSP 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_OSTIMER 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_PWM0 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_PWM1 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_PWM2 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_PWM3 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_PWRI2C 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_PXA300_GCU 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_PXA320_GCU 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_SMC 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_SSP 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_SSP1 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_SSP2 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_SSP3 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_SSP4 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_STUART 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_TOUCH 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_TPM 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_UDC 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_USB 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_USB2 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_USBH 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_USBHOST 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_USIM 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_USIM1 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_USMI0 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_OSC32k768 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_MAX 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif