Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define PLL_APLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define PLL_DPLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define PLL_CPLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define PLL_NPLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define APLL_BOOST_H		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define APLL_BOOST_L		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define ARMCLK			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* sclk gates (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define USB480M			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SCLK_PDM		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SCLK_I2S0_TX		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SCLK_I2S0_TX_OUT	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SCLK_I2S0_RX		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SCLK_I2S0_RX_OUT	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SCLK_I2S1		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SCLK_I2S1_OUT		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SCLK_I2S2		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SCLK_I2S2_OUT		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SCLK_UART1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SCLK_UART2		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SCLK_UART3		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SCLK_UART4		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SCLK_UART5		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SCLK_I2C0		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SCLK_I2C1		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SCLK_I2C2		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SCLK_I2C3		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SCLK_I2C4		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SCLK_PWM0		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SCLK_PWM1		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SCLK_SPI0		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SCLK_SPI1		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SCLK_TIMER0		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SCLK_TIMER1		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SCLK_TIMER2		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SCLK_TIMER3		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SCLK_TIMER4		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SCLK_TIMER5		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SCLK_TSADC		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SCLK_SARADC		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SCLK_OTP		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SCLK_OTP_USR		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SCLK_CRYPTO		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SCLK_CRYPTO_APK		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SCLK_DDRC		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SCLK_ISP		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SCLK_CIF_OUT		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SCLK_RGA_CORE		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SCLK_VOPB_PWM		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SCLK_NANDC		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SCLK_SDIO		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SCLK_EMMC		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SCLK_SFC		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SCLK_SDMMC		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SCLK_OTG_ADP		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SCLK_GMAC_SRC		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SCLK_GMAC		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SCLK_GMAC_RX_TX		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SCLK_MAC_REF		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SCLK_MAC_REFOUT		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SCLK_MAC_OUT		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SCLK_SDMMC_DRV		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SCLK_SDMMC_SAMPLE	68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SCLK_SDIO_DRV		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SCLK_SDIO_SAMPLE	70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SCLK_EMMC_DRV		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SCLK_EMMC_SAMPLE	72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SCLK_GPU		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SCLK_PVTM		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SCLK_CORE_VPU		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SCLK_GMAC_RMII		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SCLK_UART2_SRC		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SCLK_NANDC_DIV		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SCLK_NANDC_DIV50	79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SCLK_SDIO_DIV		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SCLK_SDIO_DIV50		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SCLK_EMMC_DIV		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SCLK_EMMC_DIV50		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SCLK_DDRCLK		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SCLK_UART1_SRC		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SCLK_SDMMC_DIV		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SCLK_SDMMC_DIV50	87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SCLK_I2S0_TX_MUX	88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SCLK_I2S0_RX_MUX	89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* dclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define DCLK_VOPB		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DCLK_VOPL		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* aclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define ACLK_GPU		170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ACLK_BUS_PRE		171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ACLK_CRYPTO		172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ACLK_VI_PRE		173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ACLK_VO_PRE		174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ACLK_VPU		175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ACLK_PERI_PRE		176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ACLK_GMAC		178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ACLK_CIF		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ACLK_ISP		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ACLK_VOPB		181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ACLK_VOPL		182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ACLK_RGA		183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ACLK_GIC		184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ACLK_DCF		186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ACLK_DMAC		187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ACLK_BUS_SRC		188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ACLK_PERI_SRC		189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* hclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HCLK_BUS_PRE		240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HCLK_CRYPTO		241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HCLK_VI_PRE		242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HCLK_VO_PRE		243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HCLK_VPU		244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HCLK_PERI_PRE		245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HCLK_MMC_NAND		246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HCLK_SDMMC		247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HCLK_USB		248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HCLK_CIF		249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HCLK_ISP		250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HCLK_VOPB		251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HCLK_VOPL		252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HCLK_RGA		253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HCLK_NANDC		254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HCLK_SDIO		255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HCLK_EMMC		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HCLK_SFC		257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HCLK_OTG		258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HCLK_HOST		259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HCLK_HOST_ARB		260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HCLK_PDM		261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HCLK_I2S0		262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HCLK_I2S1		263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HCLK_I2S2		264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* pclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PCLK_BUS_PRE		320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PCLK_DDR		321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PCLK_VO_PRE		322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PCLK_GMAC		323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PCLK_MIPI_DSI		324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PCLK_MIPIDSIPHY		325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PCLK_MIPICSIPHY		326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PCLK_USB_GRF		327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PCLK_DCF		328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PCLK_UART1		329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PCLK_UART2		330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PCLK_UART3		331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PCLK_UART4		332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PCLK_UART5		333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PCLK_I2C0		334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PCLK_I2C1		335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PCLK_I2C2		336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCLK_I2C3		337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCLK_I2C4		338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PCLK_PWM0		339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PCLK_PWM1		340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PCLK_SPI0		341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PCLK_SPI1		342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PCLK_SARADC		343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PCLK_TSADC		344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PCLK_TIMER		345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PCLK_OTP_NS		346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PCLK_WDT_NS		347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PCLK_GPIO1		348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PCLK_GPIO2		349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PCLK_GPIO3		350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PCLK_ISP		351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PCLK_CIF		352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PCLK_OTP_PHY		353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_NR_CLKS		(PCLK_OTP_PHY + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* pmu-clocks indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PLL_GPLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SCLK_RTC32K_PMU		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SCLK_WIFI_PMU		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SCLK_UART0_PMU		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SCLK_PVTM_PMU		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PCLK_PMU_PRE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SCLK_REF24M_PMU		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SCLK_USBPHY_REF		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SCLK_MIPIDSIPHY_REF	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define XIN24M_DIV		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PCLK_GPIO0_PMU		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PCLK_UART0_PMU		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLKPMU_NR_CLKS		(PCLK_UART0_PMU + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SRST_CORE0_PO		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SRST_CORE1_PO		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SRST_CORE2_PO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SRST_CORE3_PO		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SRST_CORE0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SRST_CORE1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SRST_CORE2		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SRST_CORE3		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SRST_CORE0_DBG		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SRST_CORE1_DBG		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SRST_CORE2_DBG		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SRST_CORE3_DBG		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SRST_TOPDBG		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SRST_CORE_NOC		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SRST_STRC_A		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SRST_L2C		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SRST_DAP		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SRST_CORE_PVTM		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SRST_GPU		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SRST_GPU_NIU		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SRST_UPCTL2		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SRST_UPCTL2_A		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SRST_UPCTL2_P		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SRST_MSCH		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SRST_MSCH_P		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SRST_DDRMON_P		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SRST_DDRSTDBY_P		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SRST_DDRSTDBY		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SRST_DDRGRF_p		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SRST_AXI_SPLIT_A	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SRST_AXI_CMD_A		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SRST_AXI_CMD_P		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SRST_DDRPHY		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SRST_DDRPHYDIV		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SRST_DDRPHY_P		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SRST_VPU_A		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SRST_VPU_NIU_A		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SRST_VPU_H		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SRST_VPU_NIU_H		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SRST_VI_NIU_A		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SRST_VI_NIU_H		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SRST_ISP_H		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SRST_ISP		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SRST_CIF_A		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SRST_CIF_H		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SRST_CIF_PCLKIN		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SRST_MIPICSIPHY_P	47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SRST_VO_NIU_A		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SRST_VO_NIU_H		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SRST_VO_NIU_P		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SRST_VOPB_A		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SRST_VOPB_H		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SRST_VOPB		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SRST_PWM_VOPB		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SRST_VOPL_A		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SRST_VOPL_H		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SRST_VOPL		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SRST_RGA_A		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SRST_RGA_H		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SRST_RGA		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SRST_MIPIDSI_HOST_P	61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SRST_MIPIDSIPHY_P	62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SRST_VPU_CORE		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SRST_PERI_NIU_A		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SRST_USB_NIU_H		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SRST_USB2OTG_H		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SRST_USB2OTG		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SRST_USB2OTG_ADP	68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SRST_USB2HOST_H		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SRST_USB2HOST_ARB_H	70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SRST_USB2HOST_AUX_H	71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SRST_USB2HOST_EHCI	72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SRST_USB2HOST		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SRST_USBPHYPOR		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SRST_USBPHY_OTG_PORT	75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SRST_USBPHY_HOST_PORT	76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SRST_USBPHY_GRF		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SRST_CPU_BOOST_P	78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SRST_CPU_BOOST		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SRST_MMC_NAND_NIU_H	80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SRST_SDIO_H		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SRST_EMMC_H		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SRST_SFC_H		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SRST_SFC		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SRST_SDCARD_NIU_H	85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SRST_SDMMC_H		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SRST_NANDC_H		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SRST_NANDC		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SRST_GMAC_NIU_A		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SRST_GMAC_NIU_P		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SRST_GMAC_A		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SRST_PMU_NIU_P		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SRST_PMU_SGRF_P		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SRST_PMU_GRF_P		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SRST_PMU		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SRST_PMU_MEM_P		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SRST_PMU_GPIO0_P	101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SRST_PMU_UART0_P	102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SRST_PMU_CRU_P		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SRST_PMU_PVTM		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SRST_PMU_UART		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SRST_PMU_NIU_H		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SRST_PMU_DDR_FAIL_SAVE	107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SRST_PMU_CORE_PERF_A	108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SRST_PMU_CORE_GRF_P	109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SRST_PMU_GPU_PERF_A	110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SRST_PMU_GPU_GRF_P	111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SRST_CRYPTO_NIU_A	112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SRST_CRYPTO_NIU_H	113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SRST_CRYPTO_A		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SRST_CRYPTO_H		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SRST_CRYPTO		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SRST_CRYPTO_APK		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SRST_BUS_NIU_H		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SRST_USB_NIU_P		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SRST_BUS_TOP_NIU_P	122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SRST_INTMEM_A		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SRST_GIC_A		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SRST_ROM_H		126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SRST_DCF_A		127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SRST_DCF_P		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SRST_PDM_H		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SRST_PDM		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SRST_I2S0_H		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SRST_I2S0_TX		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SRST_I2S1_H		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SRST_I2S1		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SRST_I2S2_H		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SRST_I2S2		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SRST_UART1_P		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SRST_UART1		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SRST_UART2_P		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SRST_UART2		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SRST_UART3_P		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SRST_UART3		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SRST_UART4_P		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SRST_UART4		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SRST_UART5_P		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SRST_UART5		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SRST_I2C0_P		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SRST_I2C0		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SRST_I2C1_P		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SRST_I2C1		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SRST_I2C2_P		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SRST_I2C2		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SRST_I2C3_P		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SRST_I2C3		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SRST_PWM0_P		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SRST_PWM0		158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SRST_PWM1_P		159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SRST_PWM1		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SRST_SPI0_P		161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SRST_SPI0		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SRST_SPI1_P		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SRST_SPI1		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SRST_SARADC_P		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SRST_SARADC		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SRST_TSADC_P		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SRST_TSADC		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SRST_TIMER_P		169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SRST_TIMER0		170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SRST_TIMER1		171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SRST_TIMER2		172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SRST_TIMER3		173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SRST_TIMER4		174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SRST_TIMER5		175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SRST_OTP_NS_P		176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SRST_OTP_NS_SBPI	177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SRST_OTP_NS_USR		178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SRST_OTP_PHY_P		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SRST_OTP_PHY		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SRST_WDT_NS_P		181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SRST_GPIO1_P		182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SRST_GPIO2_P		183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SRST_GPIO3_P		184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SRST_SGRF_P		185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SRST_GRF_P		186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SRST_I2S0_RX		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SRST_I2S0_RX_S		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SRST_DCF_P_S		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #endif