Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_CLOCK_PISTACHIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /* PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define CLK_MIPS_PLL			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define CLK_AUDIO_PLL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CLK_RPU_V_PLL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CLK_RPU_L_PLL			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CLK_SYS_PLL			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CLK_WIFI_PLL			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CLK_BT_PLL			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* Fixed-factor clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLK_WIFI_DIV4			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CLK_WIFI_DIV8			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLK_MIPS			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLK_AUDIO_IN			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_AUDIO			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_I2S				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_SPDIF			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLK_AUDIO_DAC			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_RPU_V			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLK_RPU_L			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_RPU_SLEEP			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLK_WIFI_PLL_GATE		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CLK_RPU_CORE			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CLK_WIFI_ADC			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CLK_WIFI_DAC			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_USB_PHY			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_ENET_IN			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_ENET			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_UART0			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_UART1			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_PERIPH_SYS			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_SPI0			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_SPI1			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_EVENT_TIMER			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_AUX_ADC_INTERNAL		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_AUX_ADC			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_SD_HOST			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_BT				57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_BT_DIV4			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_BT_DIV8			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CLK_BT_1MHZ			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* Divider clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_MIPS_INTERNAL_DIV		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CLK_MIPS_DIV			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CLK_AUDIO_DIV			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CLK_I2S_DIV			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLK_SPDIF_DIV			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_AUDIO_DAC_DIV		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_RPU_V_DIV			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_RPU_L_DIV			71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_RPU_SLEEP_DIV		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_RPU_CORE_DIV		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_USB_PHY_DIV			74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_ENET_DIV			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLK_UART0_INTERNAL_DIV		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_UART0_DIV			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_UART1_INTERNAL_DIV		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_UART1_DIV			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_SYS_INTERNAL_DIV		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_SPI0_INTERNAL_DIV		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLK_SPI0_DIV			82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_SPI1_INTERNAL_DIV		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_SPI1_DIV			84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_EVENT_TIMER_INTERNAL_DIV	85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_EVENT_TIMER_DIV		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_AUX_ADC_INTERNAL_DIV	87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_AUX_ADC_DIV			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_SD_HOST_DIV			89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_BT_DIV			90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLK_BT_DIV4_DIV			91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CLK_BT_DIV8_DIV			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_BT_1MHZ_INTERNAL_DIV	93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_BT_1MHZ_DIV			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* Mux clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_AUDIO_REF_MUX		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_MIPS_PLL_MUX		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_AUDIO_PLL_MUX		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_AUDIO_MUX			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_RPU_V_PLL_MUX		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_RPU_L_PLL_MUX		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_RPU_L_MUX			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CLK_WIFI_PLL_MUX		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_WIFI_DIV4_MUX		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_WIFI_DIV8_MUX		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_RPU_CORE_MUX		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_SYS_PLL_MUX			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_ENET_MUX			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_EVENT_TIMER_MUX		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_SD_HOST_MUX			110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_BT_PLL_MUX			111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_DEBUG_MUX			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_NR_CLKS			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Peripheral gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PERIPH_CLK_SYS			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PERIPH_CLK_SYS_BUS		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PERIPH_CLK_DDR			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PERIPH_CLK_ROM			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PERIPH_CLK_COUNTER_FAST		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PERIPH_CLK_COUNTER_SLOW		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PERIPH_CLK_IR			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PERIPH_CLK_WD			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PERIPH_CLK_PDM			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PERIPH_CLK_PWM			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PERIPH_CLK_I2C0			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PERIPH_CLK_I2C1			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PERIPH_CLK_I2C2			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PERIPH_CLK_I2C3			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Peripheral divider clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PERIPH_CLK_ROM_DIV		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PERIPH_CLK_COUNTER_FAST_DIV	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PERIPH_CLK_COUNTER_SLOW_PRE_DIV	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PERIPH_CLK_COUNTER_SLOW_DIV	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PERIPH_CLK_IR_PRE_DIV		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PERIPH_CLK_IR_DIV		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PERIPH_CLK_WD_PRE_DIV		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PERIPH_CLK_WD_DIV		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PERIPH_CLK_PDM_PRE_DIV		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PERIPH_CLK_PDM_DIV		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PERIPH_CLK_PWM_PRE_DIV		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PERIPH_CLK_PWM_DIV		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PERIPH_CLK_I2C0_PRE_DIV		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PERIPH_CLK_I2C0_DIV		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PERIPH_CLK_I2C1_PRE_DIV		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PERIPH_CLK_I2C1_DIV		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PERIPH_CLK_I2C2_PRE_DIV		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PERIPH_CLK_I2C2_DIV		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PERIPH_CLK_I2C3_PRE_DIV		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PERIPH_CLK_I2C3_DIV		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PERIPH_CLK_NR_CLKS		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* System gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SYS_CLK_I2C0			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SYS_CLK_I2C1			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SYS_CLK_I2C2			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SYS_CLK_I2C3			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SYS_CLK_I2S_IN			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SYS_CLK_PAUD_OUT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SYS_CLK_SPDIF_OUT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SYS_CLK_SPI0_MASTER		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SYS_CLK_SPI0_SLAVE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SYS_CLK_PWM			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SYS_CLK_UART0			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SYS_CLK_UART1			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SYS_CLK_SPI1			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SYS_CLK_MDC			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SYS_CLK_SD_HOST			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SYS_CLK_ENET			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SYS_CLK_IR			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SYS_CLK_WD			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SYS_CLK_TIMER			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SYS_CLK_I2S_OUT			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SYS_CLK_SPDIF_IN		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SYS_CLK_EVENT_TIMER		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SYS_CLK_HASH			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SYS_CLK_NR_CLKS			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Gates for external input clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EXT_CLK_AUDIO_IN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EXT_CLK_ENET_IN			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EXT_CLK_NR_CLKS			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */