^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef DT_CLOCK_OXSEMI_OX820_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define DT_CLOCK_OXSEMI_OX820_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CLK_820_PLLA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLK_820_PLLB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Gate Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_820_LEON 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_820_DMA_SGDMA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_820_CIPHER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_820_SD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_820_SATA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_820_AUDIO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_820_USBMPH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_820_ETHA 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_820_PCIEA 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_820_NAND 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_820_PCIEB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_820_ETHB 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_820_REF600 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_820_USBDEV 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif /* DT_CLOCK_OXSEMI_OX820_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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