^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2017 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __DT_BINDINGS_CLK_OMAP5_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __DT_BINDINGS_CLK_OMAP5_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define OMAP5_CLKCTRL_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* mpu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* dsp clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* abe clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* l3main1 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* l3main2 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* ipu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* dma clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* emif clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* l4cfg clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* l3instr clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* l4per clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* l4_secure clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* iva clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* dss clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* gpu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* l3init clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* wkupaon clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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