^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2017 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __DT_BINDINGS_CLK_OMAP4_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __DT_BINDINGS_CLK_OMAP4_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define OMAP4_CLKCTRL_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* mpuss clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* tesla clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* abe clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* l4_ao clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* l3_1 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* l3_2 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* ducati clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* l3_dma clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* l3_emif clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* d2d clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* l4_cfg clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* l3_instr clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* ivahd clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* iss clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* l3_dss clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* l3_gfx clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* l3_init clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* l4_per clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* l4_secure clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* l4_wkup clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* emu_sys clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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