Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_MT8183_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_MT8183_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* APMIXED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define CLK_APMIXED_ARMPLL_LL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CLK_APMIXED_ARMPLL_L		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CLK_APMIXED_CCIPLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CLK_APMIXED_MAINPLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CLK_APMIXED_UNIV2PLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CLK_APMIXED_MSDCPLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CLK_APMIXED_MMPLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CLK_APMIXED_MFGPLL		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLK_APMIXED_TVDPLL		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CLK_APMIXED_APLL1		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CLK_APMIXED_APLL2		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CLK_APMIXED_SSUSB_26M		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLK_APMIXED_APPLL_26M		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLK_APMIXED_MIPIC0_26M		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_APMIXED_MDPLLGP_26M		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_APMIXED_MMSYS_26M		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_APMIXED_UFS_26M		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLK_APMIXED_MIPIC1_26M		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_APMIXED_MEMPLL_26M		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLK_APMIXED_CLKSQ_LVPLL_26M	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_APMIXED_MIPID0_26M		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLK_APMIXED_MIPID1_26M		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CLK_APMIXED_NR_CLK		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* TOPCKGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_TOP_MUX_AXI			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_TOP_MUX_MM			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_TOP_MUX_CAM			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_TOP_MUX_MFG			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_TOP_MUX_CAMTG		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_TOP_MUX_UART		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_TOP_MUX_SPI			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_TOP_MUX_MSDC50_0_HCLK	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_TOP_MUX_MSDC50_0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_TOP_MUX_MSDC30_1		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_TOP_MUX_MSDC30_2		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_TOP_MUX_AUDIO		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_TOP_MUX_AUD_INTBUS		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_TOP_MUX_FPWRAP_ULPOSC	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_TOP_MUX_SCP			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CLK_TOP_MUX_ATB			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CLK_TOP_MUX_SSPM		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CLK_TOP_MUX_DPI0		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_TOP_MUX_SCAM		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CLK_TOP_MUX_AUD_1		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CLK_TOP_MUX_AUD_2		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CLK_TOP_MUX_DISP_PWM		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLK_TOP_MUX_SSUSB_TOP_XHCI	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_TOP_MUX_USB_TOP		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_TOP_MUX_SPM			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_TOP_MUX_I2C			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_TOP_MUX_F52M_MFG		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_TOP_MUX_SENINF		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_TOP_MUX_DXCC		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_TOP_MUX_CAMTG2		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLK_TOP_MUX_AUD_ENG1		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_TOP_MUX_AUD_ENG2		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_TOP_MUX_FAES_UFSFDE		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_TOP_MUX_FUFS		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_TOP_MUX_IMG			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_TOP_MUX_DSP			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLK_TOP_MUX_DSP1		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_TOP_MUX_DSP2		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_TOP_MUX_IPU_IF		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_TOP_MUX_CAMTG3		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_TOP_MUX_CAMTG4		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_TOP_MUX_PMICSPI		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_TOP_SYSPLL_CK		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_TOP_SYSPLL_D2		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_TOP_SYSPLL_D3		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLK_TOP_SYSPLL_D5		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CLK_TOP_SYSPLL_D7		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_TOP_SYSPLL_D2_D2		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_TOP_SYSPLL_D2_D4		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLK_TOP_SYSPLL_D2_D8		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CLK_TOP_SYSPLL_D2_D16		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_TOP_SYSPLL_D3_D2		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_TOP_SYSPLL_D3_D4		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_TOP_SYSPLL_D3_D8		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_TOP_SYSPLL_D5_D2		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_TOP_SYSPLL_D5_D4		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_TOP_SYSPLL_D7_D2		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_TOP_SYSPLL_D7_D4		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CLK_TOP_UNIVPLL_CK		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_TOP_UNIVPLL_D2		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_TOP_UNIVPLL_D3		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_TOP_UNIVPLL_D5		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_TOP_UNIVPLL_D7		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_TOP_UNIVPLL_D2_D2		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_TOP_UNIVPLL_D2_D4		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_TOP_UNIVPLL_D2_D8		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_TOP_UNIVPLL_D3_D2		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_TOP_UNIVPLL_D3_D4		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_TOP_UNIVPLL_D3_D8		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_TOP_UNIVPLL_D5_D2		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_TOP_UNIVPLL_D5_D4		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_TOP_UNIVPLL_D5_D8		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_TOP_APLL1_CK		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_TOP_APLL1_D2		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_TOP_APLL1_D4		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_TOP_APLL1_D8		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_TOP_APLL2_CK		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_TOP_APLL2_D2		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_TOP_APLL2_D4		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_TOP_APLL2_D8		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_TOP_TVDPLL_CK		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_TOP_TVDPLL_D2		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_TOP_TVDPLL_D4		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_TOP_TVDPLL_D8		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_TOP_TVDPLL_D16		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_TOP_MSDCPLL_CK		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_TOP_MSDCPLL_D2		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_TOP_MSDCPLL_D4		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_TOP_MSDCPLL_D8		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_TOP_MSDCPLL_D16		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_TOP_AD_OSC_CK		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_TOP_OSC_D2			91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_TOP_OSC_D4			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_TOP_OSC_D8			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_TOP_OSC_D16			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_TOP_F26M_CK_D2		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_TOP_MFGPLL_CK		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_TOP_UNIVP_192M_CK		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_TOP_UNIVP_192M_D2		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_TOP_UNIVP_192M_D4		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_TOP_UNIVP_192M_D8		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_TOP_UNIVP_192M_D16		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_TOP_UNIVP_192M_D32		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_TOP_MMPLL_CK		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_TOP_MMPLL_D4		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_TOP_MMPLL_D4_D2		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_TOP_MMPLL_D4_D4		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_TOP_MMPLL_D5		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_TOP_MMPLL_D5_D2		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_TOP_MMPLL_D5_D4		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_TOP_MMPLL_D6		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_TOP_MMPLL_D7		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_TOP_CLK26M			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_TOP_CLK13M			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_TOP_ULPOSC			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_TOP_UNIVP_192M		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_TOP_MUX_APLL_I2S0		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_TOP_MUX_APLL_I2S1		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_TOP_MUX_APLL_I2S2		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_TOP_MUX_APLL_I2S3		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_TOP_MUX_APLL_I2S4		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_TOP_MUX_APLL_I2S5		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_TOP_APLL12_DIV0		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_TOP_APLL12_DIV1		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_TOP_APLL12_DIV2		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_TOP_APLL12_DIV3		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_TOP_APLL12_DIV4		126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_TOP_APLL12_DIVB		127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_TOP_UNIVPLL			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_TOP_ARMPLL_DIV_PLL1		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_TOP_ARMPLL_DIV_PLL2		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_TOP_UNIVPLL_D3_D16		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_TOP_NR_CLK			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* CAMSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_CAM_LARB6			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_CAM_DFP_VAD			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_CAM_CAM			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_CAM_CAMTG			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_CAM_SENINF			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_CAM_CAMSV0			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_CAM_CAMSV1			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_CAM_CAMSV2			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_CAM_CCU			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_CAM_LARB3			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_CAM_NR_CLK			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* INFRACFG_AO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_INFRA_PMIC_TMR		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_INFRA_PMIC_AP		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_INFRA_PMIC_MD		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_INFRA_PMIC_CONN		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_INFRA_SCPSYS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_INFRA_SEJ			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_INFRA_APXGPT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_INFRA_ICUSB			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_INFRA_GCE			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_INFRA_THERM			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_INFRA_I2C0			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_INFRA_I2C1			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_INFRA_I2C2			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_INFRA_I2C3			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_INFRA_PWM_HCLK		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_INFRA_PWM1			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_INFRA_PWM2			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_INFRA_PWM3			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_INFRA_PWM4			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_INFRA_PWM			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_INFRA_UART0			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_INFRA_UART1			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_INFRA_UART2			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_INFRA_UART3			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_INFRA_GCE_26M		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_INFRA_CQ_DMA_FPC		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_INFRA_BTIF			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_INFRA_SPI0			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_INFRA_MSDC0			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_INFRA_MSDC1			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_INFRA_MSDC2			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_INFRA_MSDC0_SCK		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_INFRA_DVFSRC		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_INFRA_GCPU			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_INFRA_TRNG			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_INFRA_AUXADC		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_INFRA_CPUM			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_INFRA_CCIF1_AP		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_INFRA_CCIF1_MD		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_INFRA_AUXADC_MD		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_INFRA_MSDC1_SCK		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_INFRA_MSDC2_SCK		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_INFRA_AP_DMA		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_INFRA_XIU			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_INFRA_DEVICE_APC		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_INFRA_CCIF_AP		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_INFRA_DEBUGSYS		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_INFRA_AUDIO			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_INFRA_CCIF_MD		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_INFRA_DXCC_SEC_CORE		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_INFRA_DXCC_AO		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_INFRA_DRAMC_F26M		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_INFRA_IRTX			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_INFRA_DISP_PWM		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_INFRA_CLDMA_BCLK		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_INFRA_AUDIO_26M_BCLK	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_INFRA_SPI1			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_INFRA_I2C4			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_INFRA_MODEM_TEMP_SHARE	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLK_INFRA_SPI2			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLK_INFRA_SPI3			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_INFRA_UNIPRO_SCK		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_INFRA_UNIPRO_TICK		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_INFRA_UFS_MP_SAP_BCLK	63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_INFRA_MD32_BCLK		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_INFRA_SSPM			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_INFRA_UNIPRO_MBIST		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_INFRA_SSPM_BUS_HCLK		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_INFRA_I2C5			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_INFRA_I2C5_ARBITER		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CLK_INFRA_I2C5_IMM		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_INFRA_I2C1_ARBITER		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_INFRA_I2C1_IMM		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_INFRA_I2C2_ARBITER		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_INFRA_I2C2_IMM		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_INFRA_SPI4			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_INFRA_SPI5			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_INFRA_CQ_DMA		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_INFRA_UFS			78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_INFRA_AES_UFSFDE		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLK_INFRA_UFS_TICK		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLK_INFRA_MSDC0_SELF		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_INFRA_MSDC1_SELF		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK_INFRA_MSDC2_SELF		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_INFRA_SSPM_26M_SELF		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_INFRA_SSPM_32K_SELF		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_INFRA_UFS_AXI		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_INFRA_I2C6			87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLK_INFRA_AP_MSDC0		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_INFRA_MD_MSDC0		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLK_INFRA_USB			90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_INFRA_DEVMPU_BCLK		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_INFRA_CCIF2_AP		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_INFRA_CCIF2_MD		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_INFRA_CCIF3_AP		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_INFRA_CCIF3_MD		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CLK_INFRA_SEJ_F13M		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_INFRA_AES_BCLK		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CLK_INFRA_I2C7			98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CLK_INFRA_I2C8			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CLK_INFRA_FBIST2FPC		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CLK_INFRA_NR_CLK		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* PERICFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CLK_PERI_AXI			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CLK_PERI_NR_CLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* MFGCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CLK_MFG_BG3D			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CLK_MFG_NR_CLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* IMG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CLK_IMG_OWE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CLK_IMG_WPE_B			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CLK_IMG_WPE_A			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CLK_IMG_MFB			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CLK_IMG_RSC			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CLK_IMG_DPE			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CLK_IMG_FDVT			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CLK_IMG_DIP			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CLK_IMG_LARB2			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CLK_IMG_LARB5			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CLK_IMG_NR_CLK			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* MMSYS_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CLK_MM_SMI_COMMON		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CLK_MM_SMI_LARB0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CLK_MM_SMI_LARB1		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CLK_MM_GALS_COMM0		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CLK_MM_GALS_COMM1		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CLK_MM_GALS_CCU2MM		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CLK_MM_GALS_IPU12MM		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CLK_MM_GALS_IMG2MM		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CLK_MM_GALS_CAM2MM		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CLK_MM_GALS_IPU2MM		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CLK_MM_MDP_DL_TXCK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CLK_MM_IPU_DL_TXCK		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CLK_MM_MDP_RDMA0		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CLK_MM_MDP_RDMA1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CLK_MM_MDP_RSZ0			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLK_MM_MDP_RSZ1			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CLK_MM_MDP_TDSHP		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CLK_MM_MDP_WROT0		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CLK_MM_FAKE_ENG			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CLK_MM_DISP_OVL0		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CLK_MM_DISP_OVL0_2L		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CLK_MM_DISP_OVL1_2L		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CLK_MM_DISP_RDMA0		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CLK_MM_DISP_RDMA1		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CLK_MM_DISP_WDMA0		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CLK_MM_DISP_COLOR0		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CLK_MM_DISP_CCORR0		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CLK_MM_DISP_AAL0		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CLK_MM_DISP_GAMMA0		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CLK_MM_DISP_DITHER0		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CLK_MM_DISP_SPLIT		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CLK_MM_DSI0_MM			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CLK_MM_DSI0_IF			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CLK_MM_DPI_MM			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CLK_MM_DPI_IF			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CLK_MM_FAKE_ENG2		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CLK_MM_MDP_DL_RX		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CLK_MM_IPU_DL_RX		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define CLK_MM_26M			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CLK_MM_MMSYS_R2Y		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CLK_MM_DISP_RSZ			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define CLK_MM_MDP_WDMA0		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define CLK_MM_MDP_AAL			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CLK_MM_MDP_CCORR		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CLK_MM_DBI_MM			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CLK_MM_DBI_IF			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CLK_MM_NR_CLK			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* VDEC_GCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CLK_VDEC_VDEC			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CLK_VDEC_LARB1			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CLK_VDEC_NR_CLK			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* VENC_GCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CLK_VENC_LARB			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CLK_VENC_VENC			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define CLK_VENC_JPGENC			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CLK_VENC_NR_CLK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* AUDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CLK_AUDIO_TML			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CLK_AUDIO_DAC_PREDIS		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define CLK_AUDIO_DAC			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CLK_AUDIO_ADC			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CLK_AUDIO_APLL_TUNER		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CLK_AUDIO_APLL2_TUNER		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CLK_AUDIO_24M			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CLK_AUDIO_22M			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CLK_AUDIO_AFE			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CLK_AUDIO_I2S4			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CLK_AUDIO_I2S3			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CLK_AUDIO_I2S2			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CLK_AUDIO_I2S1			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CLK_AUDIO_PDN_ADDA6_ADC		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CLK_AUDIO_TDM			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CLK_AUDIO_NR_CLK		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* IPU_CONN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define CLK_IPU_CONN_IPU		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CLK_IPU_CONN_AHB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CLK_IPU_CONN_AXI		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CLK_IPU_CONN_ISP		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CLK_IPU_CONN_CAM_ADL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CLK_IPU_CONN_IMG_ADL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define CLK_IPU_CONN_DAP_RX		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CLK_IPU_CONN_APB2AXI		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CLK_IPU_CONN_APB2AHB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CLK_IPU_CONN_IPU_CAB1TO2	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CLK_IPU_CONN_IPU1_CAB1TO2	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CLK_IPU_CONN_IPU2_CAB1TO2	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CLK_IPU_CONN_CAB3TO3		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CLK_IPU_CONN_CAB2TO1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define CLK_IPU_CONN_CAB3TO1_SLICE	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define CLK_IPU_CONN_NR_CLK		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* IPU_ADL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define CLK_IPU_ADL_CABGEN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define CLK_IPU_ADL_NR_CLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* IPU_CORE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CLK_IPU_CORE0_JTAG		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CLK_IPU_CORE0_AXI		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CLK_IPU_CORE0_IPU		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CLK_IPU_CORE0_NR_CLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* IPU_CORE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CLK_IPU_CORE1_JTAG		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CLK_IPU_CORE1_AXI		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define CLK_IPU_CORE1_IPU		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define CLK_IPU_CORE1_NR_CLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* MCUCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CLK_MCU_MP0_SEL			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CLK_MCU_MP2_SEL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define CLK_MCU_BUS_SEL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CLK_MCU_NR_CLK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #endif /* _DT_BINDINGS_CLK_MT8183_H */