^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_MT8173_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_MT8173_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* TOPCKGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_TOP_CLKPH_MCK_O 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_TOP_USB_SYSPLL_125M 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_TOP_HDMITX_DIG_CTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_TOP_ARMCA7PLL_754M 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_TOP_ARMCA7PLL_502M 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_TOP_MAIN_H546M 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_TOP_MAIN_H364M 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_TOP_MAIN_H218P4M 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_TOP_MAIN_H156M 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_TOP_TVDPLL_445P5M 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_TOP_TVDPLL_594M 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_TOP_UNIV_624M 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_TOP_UNIV_416M 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_TOP_UNIV_249P6M 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_TOP_UNIV_178P3M 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_TOP_UNIV_48M 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_TOP_CLKRTC_EXT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_TOP_CLKRTC_INT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_TOP_FPC 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_TOP_HDMITXPLL_D2 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_TOP_HDMITXPLL_D3 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_TOP_ARMCA7PLL_D2 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_TOP_ARMCA7PLL_D3 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_TOP_APLL1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_TOP_APLL2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_TOP_DMPLL 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_TOP_DMPLL_D2 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_TOP_DMPLL_D4 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_TOP_DMPLL_D8 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_TOP_DMPLL_D16 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_TOP_LVDSPLL_D2 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_TOP_LVDSPLL_D4 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_TOP_LVDSPLL_D8 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_TOP_MMPLL 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_TOP_MMPLL_D2 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_TOP_MSDCPLL 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_TOP_MSDCPLL_D2 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_TOP_MSDCPLL_D4 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_TOP_MSDCPLL2 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_TOP_MSDCPLL2_D2 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_TOP_MSDCPLL2_D4 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_TOP_SYSPLL_D2 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_TOP_SYSPLL1_D2 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_TOP_SYSPLL1_D4 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_TOP_SYSPLL1_D8 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_TOP_SYSPLL1_D16 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_TOP_SYSPLL_D3 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_TOP_SYSPLL2_D2 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_TOP_SYSPLL2_D4 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_TOP_SYSPLL_D5 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_TOP_SYSPLL3_D2 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_TOP_SYSPLL3_D4 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_TOP_SYSPLL_D7 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_TOP_SYSPLL4_D2 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_TOP_SYSPLL4_D4 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_TOP_TVDPLL 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_TOP_TVDPLL_D2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_TOP_TVDPLL_D4 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_TOP_TVDPLL_D8 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_TOP_TVDPLL_D16 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_TOP_UNIVPLL_D2 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_TOP_UNIVPLL1_D2 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_TOP_UNIVPLL1_D4 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_TOP_UNIVPLL1_D8 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_TOP_UNIVPLL_D3 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_TOP_UNIVPLL2_D2 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_TOP_UNIVPLL2_D4 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_TOP_UNIVPLL2_D8 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_TOP_UNIVPLL_D5 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_TOP_UNIVPLL3_D2 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_TOP_UNIVPLL3_D4 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_TOP_UNIVPLL3_D8 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_TOP_UNIVPLL_D7 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_TOP_UNIVPLL_D26 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_TOP_UNIVPLL_D52 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_TOP_VCODECPLL 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_TOP_VCODECPLL_370P5 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLK_TOP_VENCPLL 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_TOP_VENCPLL_D2 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_TOP_VENCPLL_D4 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_TOP_AXI_SEL 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_TOP_MEM_SEL 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_TOP_DDRPHYCFG_SEL 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_TOP_MM_SEL 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_TOP_PWM_SEL 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_TOP_VDEC_SEL 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_TOP_VENC_SEL 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_TOP_MFG_SEL 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_TOP_CAMTG_SEL 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_TOP_UART_SEL 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_TOP_SPI_SEL 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_TOP_USB20_SEL 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_TOP_USB30_SEL 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_TOP_MSDC50_0_H_SEL 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_TOP_MSDC50_0_SEL 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_TOP_MSDC30_1_SEL 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_TOP_MSDC30_2_SEL 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_TOP_MSDC30_3_SEL 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_TOP_AUDIO_SEL 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_TOP_AUD_INTBUS_SEL 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_TOP_PMICSPI_SEL 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_TOP_SCP_SEL 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_TOP_ATB_SEL 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_TOP_VENC_LT_SEL 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_TOP_DPI0_SEL 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_TOP_IRDA_SEL 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_TOP_CCI400_SEL 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_TOP_AUD_1_SEL 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_TOP_AUD_2_SEL 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_TOP_MEM_MFG_IN_SEL 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_TOP_AXI_MFG_IN_SEL 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_TOP_SCAM_SEL 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_TOP_SPINFI_IFR_SEL 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_TOP_HDMI_SEL 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_TOP_DPILVDS_SEL 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_TOP_MSDC50_2_H_SEL 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_TOP_HDCP_SEL 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_TOP_HDCP_24M_SEL 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_TOP_RTC_SEL 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_TOP_APLL1_DIV0 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_TOP_APLL1_DIV1 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_TOP_APLL1_DIV2 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_TOP_APLL1_DIV3 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_TOP_APLL1_DIV4 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_TOP_APLL1_DIV5 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_TOP_APLL2_DIV0 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_TOP_APLL2_DIV1 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_TOP_APLL2_DIV2 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_TOP_APLL2_DIV3 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_TOP_APLL2_DIV4 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_TOP_APLL2_DIV5 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_TOP_I2S0_M_SEL 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_TOP_I2S1_M_SEL 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_TOP_I2S2_M_SEL 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_TOP_I2S3_M_SEL 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_TOP_I2S3_B_SEL 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_TOP_DSI0_DIG 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_TOP_DSI1_DIG 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_TOP_LVDS_PXL 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_TOP_LVDS_CTS 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_TOP_NR_CLK 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* APMIXED_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_APMIXED_ARMCA15PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_APMIXED_ARMCA7PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_APMIXED_MAINPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_APMIXED_UNIVPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_APMIXED_MMPLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_APMIXED_MSDCPLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_APMIXED_VENCPLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_APMIXED_TVDPLL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_APMIXED_MPLL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_APMIXED_VCODECPLL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_APMIXED_APLL1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_APMIXED_APLL2 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_APMIXED_LVDSPLL 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_APMIXED_MSDCPLL2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_APMIXED_REF2USB_TX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_APMIXED_HDMI_REF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_APMIXED_NR_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* INFRA_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_INFRA_DBGCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_INFRA_SMI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_INFRA_AUDIO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_INFRA_GCE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_INFRA_L2C_SRAM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_INFRA_M4U 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_INFRA_CPUM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_INFRA_KP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_INFRA_CEC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_INFRA_PMICSPI 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_INFRA_PMICWRAP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_INFRA_CLK_13M 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_INFRA_CA53SEL 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_INFRA_CA57SEL 14 /* Deprecated. Don't use it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_INFRA_CA72SEL 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_INFRA_NR_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* PERI_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_PERI_NFI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_PERI_THERM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_PERI_PWM1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_PERI_PWM2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_PERI_PWM3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_PERI_PWM4 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_PERI_PWM5 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_PERI_PWM6 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_PERI_PWM7 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_PERI_PWM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_PERI_USB0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_PERI_USB1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_PERI_AP_DMA 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_PERI_MSDC30_0 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_PERI_MSDC30_1 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_PERI_MSDC30_2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_PERI_MSDC30_3 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_PERI_NLI_ARB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_PERI_IRDA 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_PERI_UART0 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_PERI_UART1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_PERI_UART2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_PERI_UART3 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_PERI_I2C0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_PERI_I2C1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_PERI_I2C2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_PERI_I2C3 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_PERI_I2C4 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_PERI_AUXADC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_PERI_SPI0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_PERI_I2C5 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_PERI_NFIECC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_PERI_SPI 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_PERI_IRRX 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_PERI_I2C6 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_PERI_UART0_SEL 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_PERI_UART1_SEL 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_PERI_UART2_SEL 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_PERI_UART3_SEL 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_PERI_NR_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* IMG_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_IMG_LARB2_SMI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_IMG_CAM_SMI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_IMG_CAM_CAM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_IMG_SEN_TG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_IMG_SEN_CAM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLK_IMG_CAM_SV 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLK_IMG_FD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_IMG_NR_CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* MM_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_MM_SMI_COMMON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_MM_SMI_LARB0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_MM_CAM_MDP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_MM_MDP_RDMA0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_MM_MDP_RDMA1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CLK_MM_MDP_RSZ0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_MM_MDP_RSZ1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_MM_MDP_RSZ2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_MM_MDP_TDSHP0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_MM_MDP_TDSHP1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_MM_MDP_WDMA 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_MM_MDP_WROT0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_MM_MDP_WROT1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_MM_FAKE_ENG 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_MM_MUTEX_32K 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLK_MM_DISP_OVL0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLK_MM_DISP_OVL1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_MM_DISP_RDMA0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK_MM_DISP_RDMA1 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_MM_DISP_RDMA2 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_MM_DISP_WDMA0 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_MM_DISP_WDMA1 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_MM_DISP_COLOR0 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLK_MM_DISP_COLOR1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_MM_DISP_AAL 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLK_MM_DISP_GAMMA 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_MM_DISP_UFOE 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_MM_DISP_SPLIT0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_MM_DISP_SPLIT1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_MM_DISP_MERGE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_MM_DISP_OD 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CLK_MM_DISP_PWM0MM 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_MM_DISP_PWM026M 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CLK_MM_DISP_PWM1MM 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CLK_MM_DISP_PWM126M 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CLK_MM_DSI0_ENGINE 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CLK_MM_DSI0_DIGITAL 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CLK_MM_DSI1_ENGINE 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CLK_MM_DSI1_DIGITAL 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CLK_MM_DPI_PIXEL 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CLK_MM_DPI_ENGINE 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CLK_MM_DPI1_PIXEL 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CLK_MM_DPI1_ENGINE 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CLK_MM_HDMI_PIXEL 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CLK_MM_HDMI_PLLCK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CLK_MM_HDMI_AUDIO 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CLK_MM_HDMI_SPDIF 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CLK_MM_LVDS_PIXEL 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CLK_MM_LVDS_CTS 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CLK_MM_SMI_LARB4 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CLK_MM_HDMI_HDCP 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CLK_MM_HDMI_HDCP24M 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CLK_MM_NR_CLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* VDEC_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CLK_VDEC_CKEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CLK_VDEC_LARB_CKEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CLK_VDEC_NR_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* VENC_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CLK_VENC_CKE0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CLK_VENC_CKE1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CLK_VENC_CKE2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CLK_VENC_CKE3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CLK_VENC_NR_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* VENCLT_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CLK_VENCLT_CKE0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CLK_VENCLT_CKE1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CLK_VENCLT_NR_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif /* _DT_BINDINGS_CLK_MT8173_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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