^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2020 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Fabien Parent <fparent@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _DT_BINDINGS_CLK_MT8167_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DT_BINDINGS_CLK_MT8167_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* MT8167 is based on MT8516 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/mt8516-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* APMIXEDSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_APMIXED_LVDSPLL (CLK_APMIXED_NR_CLK + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_APMIXED_HDMI_REF (CLK_APMIXED_NR_CLK + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MT8167_CLK_APMIXED_NR_CLK (CLK_APMIXED_NR_CLK + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* TOPCKGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_TOP_DSI0_LNTC_DSICK (CLK_TOP_NR_CLK + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_TOP_VPLL_DPIX (CLK_TOP_NR_CLK + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_TOP_LVDSTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_TOP_HDMTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_TOP_LVDSPLL (CLK_TOP_NR_CLK + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_TOP_LVDSPLL_D2 (CLK_TOP_NR_CLK + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_TOP_LVDSPLL_D4 (CLK_TOP_NR_CLK + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_TOP_LVDSPLL_D8 (CLK_TOP_NR_CLK + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_TOP_MIPI_26M (CLK_TOP_NR_CLK + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_TOP_TVDPLL (CLK_TOP_NR_CLK + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_TOP_TVDPLL_D4 (CLK_TOP_NR_CLK + 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_TOP_TVDPLL_D8 (CLK_TOP_NR_CLK + 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_TOP_TVDPLL_D16 (CLK_TOP_NR_CLK + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_TOP_PWM_MM (CLK_TOP_NR_CLK + 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_TOP_CAM_MM (CLK_TOP_NR_CLK + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_TOP_MFG_MM (CLK_TOP_NR_CLK + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_TOP_SPM_52M (CLK_TOP_NR_CLK + 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_TOP_MIPI_26M_DBG (CLK_TOP_NR_CLK + 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_TOP_SCAM_MM (CLK_TOP_NR_CLK + 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_TOP_SMI_MM (CLK_TOP_NR_CLK + 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_TOP_26M_HDMI_SIFM (CLK_TOP_NR_CLK + 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_TOP_26M_CEC (CLK_TOP_NR_CLK + 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_TOP_32K_CEC (CLK_TOP_NR_CLK + 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_TOP_GCPU_B (CLK_TOP_NR_CLK + 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_TOP_RG_VDEC (CLK_TOP_NR_CLK + 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_TOP_RG_FDPI0 (CLK_TOP_NR_CLK + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_TOP_RG_FDPI1 (CLK_TOP_NR_CLK + 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_TOP_RG_AXI_MFG (CLK_TOP_NR_CLK + 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_TOP_RG_SLOW_MFG (CLK_TOP_NR_CLK + 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_TOP_GFMUX_EMI1X_SEL (CLK_TOP_NR_CLK + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_TOP_CSW_MUX_MFG_SEL (CLK_TOP_NR_CLK + 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_TOP_CAMTG_MM_SEL (CLK_TOP_NR_CLK + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_TOP_PWM_MM_SEL (CLK_TOP_NR_CLK + 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_TOP_SPM_52M_SEL (CLK_TOP_NR_CLK + 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_TOP_MFG_MM_SEL (CLK_TOP_NR_CLK + 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_TOP_SMI_MM_SEL (CLK_TOP_NR_CLK + 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_TOP_SCAM_MM_SEL (CLK_TOP_NR_CLK + 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_TOP_VDEC_MM_SEL (CLK_TOP_NR_CLK + 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_TOP_DPI0_MM_SEL (CLK_TOP_NR_CLK + 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_TOP_DPI1_MM_SEL (CLK_TOP_NR_CLK + 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_TOP_AXI_MFG_IN_SEL (CLK_TOP_NR_CLK + 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_TOP_SLOW_MFG_SEL (CLK_TOP_NR_CLK + 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MT8167_CLK_TOP_NR_CLK (CLK_TOP_NR_CLK + 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* MFGCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_MFG_BAXI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_MFG_BMEM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_MFG_BG3D 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_MFG_B26M 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_MFG_NR_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* MMSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_MM_SMI_COMMON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_MM_SMI_LARB0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_MM_CAM_MDP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_MM_MDP_RDMA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_MM_MDP_RSZ0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_MM_MDP_RSZ1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_MM_MDP_TDSHP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_MM_MDP_WDMA 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_MM_MDP_WROT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_MM_FAKE_ENG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLK_MM_DISP_OVL0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_MM_DISP_RDMA0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_MM_DISP_RDMA1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_MM_DISP_WDMA 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_MM_DISP_COLOR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_MM_DISP_CCORR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_MM_DISP_AAL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_MM_DISP_GAMMA 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_MM_DISP_DITHER 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_MM_DISP_UFOE 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_MM_DISP_PWM_MM 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_MM_DISP_PWM_26M 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_MM_DSI_ENGINE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_MM_DSI_DIGITAL 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_MM_DPI0_ENGINE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_MM_DPI0_PXL 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_MM_LVDS_PXL 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_MM_LVDS_CTS 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_MM_DPI1_ENGINE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_MM_DPI1_PXL 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_MM_HDMI_PXL 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_MM_HDMI_SPDIF 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_MM_HDMI_ADSP_BCK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_MM_HDMI_PLL 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_MM_NR_CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* IMGSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_IMG_LARB1_SMI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_IMG_CAM_SMI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_IMG_CAM_CAM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_IMG_SEN_TG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_IMG_SEN_CAM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_IMG_VENC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_IMG_NR_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* VDECSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_VDEC_CKEN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_VDEC_LARB1_CKEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_VDEC_NR_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #endif /* _DT_BINDINGS_CLK_MT8167_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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