^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_MT8135_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_MT8135_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* TOPCKGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_TOP_DSI0_LNTC_DSICLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_TOP_HDMITX_CLKDIG_CTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_TOP_CLKPH_MCK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_TOP_CPUM_TCK_IN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_TOP_MAINPLL_806M 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_TOP_MAINPLL_537P3M 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_TOP_MAINPLL_322P4M 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_TOP_MAINPLL_230P3M 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_TOP_UNIVPLL_624M 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_TOP_UNIVPLL_416M 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_TOP_UNIVPLL_249P6M 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_TOP_UNIVPLL_178P3M 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_TOP_UNIVPLL_48M 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_TOP_MMPLL_D2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_TOP_MMPLL_D3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_TOP_MMPLL_D5 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_TOP_MMPLL_D7 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_TOP_MMPLL_D4 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_TOP_MMPLL_D6 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_TOP_SYSPLL_D2 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_TOP_SYSPLL_D4 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_TOP_SYSPLL_D6 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_TOP_SYSPLL_D8 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_TOP_SYSPLL_D10 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_TOP_SYSPLL_D12 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_TOP_SYSPLL_D16 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_TOP_SYSPLL_D24 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_TOP_SYSPLL_D3 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_TOP_SYSPLL_D2P5 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_TOP_SYSPLL_D5 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_TOP_SYSPLL_D3P5 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_TOP_UNIVPLL1_D2 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_TOP_UNIVPLL1_D4 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_TOP_UNIVPLL1_D6 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_TOP_UNIVPLL1_D8 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_TOP_UNIVPLL1_D10 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_TOP_UNIVPLL2_D2 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_TOP_UNIVPLL2_D4 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_TOP_UNIVPLL2_D6 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_TOP_UNIVPLL2_D8 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_TOP_UNIVPLL_D3 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_TOP_UNIVPLL_D5 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_TOP_UNIVPLL_D7 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_TOP_UNIVPLL_D10 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_TOP_UNIVPLL_D26 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_TOP_APLL 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_TOP_APLL_D4 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_TOP_APLL_D8 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_TOP_APLL_D16 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_TOP_APLL_D24 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_TOP_LVDSPLL_D2 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_TOP_LVDSPLL_D4 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_TOP_LVDSPLL_D8 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_TOP_LVDSTX_CLKDIG_CT 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_TOP_VPLL_DPIX 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_TOP_TVHDMI_H 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_TOP_HDMITX_CLKDIG_D2 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_TOP_HDMITX_CLKDIG_D3 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_TOP_TVHDMI_D2 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_TOP_TVHDMI_D4 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_TOP_MEMPLL_MCK_D4 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_TOP_AXI_SEL 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_TOP_SMI_SEL 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_TOP_MFG_SEL 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_TOP_IRDA_SEL 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_TOP_CAM_SEL 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_TOP_AUD_INTBUS_SEL 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_TOP_JPG_SEL 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_TOP_DISP_SEL 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_TOP_MSDC30_1_SEL 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_TOP_MSDC30_2_SEL 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_TOP_MSDC30_3_SEL 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_TOP_MSDC30_4_SEL 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_TOP_USB20_SEL 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_TOP_VENC_SEL 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_TOP_SPI_SEL 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_TOP_UART_SEL 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLK_TOP_MEM_SEL 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_TOP_CAMTG_SEL 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_TOP_AUDIO_SEL 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_TOP_FIX_SEL 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_TOP_VDEC_SEL 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_TOP_DDRPHYCFG_SEL 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_TOP_DPILVDS_SEL 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_TOP_PMICSPI_SEL 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_TOP_MSDC30_0_SEL 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_TOP_SMI_MFG_AS_SEL 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_TOP_GCPU_SEL 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_TOP_DPI1_SEL 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_TOP_CCI_SEL 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_TOP_APLL_SEL 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_TOP_HDMIPLL_SEL 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_TOP_NR_CLK 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* APMIXED_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_APMIXED_ARMPLL1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_APMIXED_ARMPLL2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_APMIXED_MAINPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_APMIXED_UNIVPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_APMIXED_MMPLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_APMIXED_MSDCPLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_APMIXED_TVDPLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_APMIXED_LVDSPLL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_APMIXED_AUDPLL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_APMIXED_VDECPLL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_APMIXED_NR_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* INFRA_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_INFRA_PMIC_WRAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_INFRA_PMICSPI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_INFRA_CCIF1_AP_CTRL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_INFRA_CCIF0_AP_CTRL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_INFRA_KP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_INFRA_CPUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_INFRA_M4U 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_INFRA_MFGAXI 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_INFRA_DEVAPC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_INFRA_AUDIO 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_INFRA_MFG_BUS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_INFRA_SMI 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_INFRA_DBGCLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_INFRA_NR_CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* PERI_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_PERI_I2C5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_PERI_I2C4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_PERI_I2C3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_PERI_I2C2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_PERI_I2C1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_PERI_I2C0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_PERI_UART3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_PERI_UART2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_PERI_UART1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_PERI_UART0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_PERI_IRDA 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_PERI_NLI 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_PERI_MD_HIF 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_PERI_AP_HIF 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_PERI_MSDC30_3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_PERI_MSDC30_2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_PERI_MSDC30_1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_PERI_MSDC20_2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_PERI_MSDC20_1 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_PERI_AP_DMA 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_PERI_USB1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_PERI_USB0 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_PERI_PWM 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_PERI_PWM7 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_PERI_PWM6 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_PERI_PWM5 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_PERI_PWM4 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_PERI_PWM3 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_PERI_PWM2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_PERI_PWM1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_PERI_THERM 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_PERI_NFI 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_PERI_USBSLV 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_PERI_USB1_MCU 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_PERI_USB0_MCU 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_PERI_GCPU 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_PERI_FHCTL 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_PERI_SPI1 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_PERI_AUXADC 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_PERI_PERI_PWRAP 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_PERI_I2C6 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_PERI_UART0_SEL 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_PERI_UART1_SEL 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_PERI_UART2_SEL 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_PERI_UART3_SEL 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_PERI_NR_CLK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif /* _DT_BINDINGS_CLK_MT8135_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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