Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Chen Zhong <chen.zhong@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_MT7622_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_MT7622_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* TOPCKGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CLK_TOP_TO_U2_PHY		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CLK_TOP_TO_U2_PHY_1P		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CLK_TOP_PCIE0_PIPE_EN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CLK_TOP_PCIE1_PIPE_EN		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CLK_TOP_SSUSB_TX250M		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CLK_TOP_SSUSB_EQ_RX250M		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CLK_TOP_SSUSB_CDR_REF		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLK_TOP_SSUSB_CDR_FB		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CLK_TOP_SATA_ASIC		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CLK_TOP_SATA_RBC		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CLK_TOP_TO_USB3_SYS		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLK_TOP_P1_1MHZ			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLK_TOP_4MHZ			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_TOP_P0_1MHZ			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_TOP_TXCLK_SRC_PRE		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_TOP_RTC			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLK_TOP_MEMPLL			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_TOP_DMPLL			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLK_TOP_SYSPLL_D2		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_TOP_SYSPLL1_D2		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLK_TOP_SYSPLL1_D4		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CLK_TOP_SYSPLL1_D8		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CLK_TOP_SYSPLL2_D4		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CLK_TOP_SYSPLL2_D8		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_TOP_SYSPLL_D5		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_TOP_SYSPLL3_D2		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_TOP_SYSPLL3_D4		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_TOP_SYSPLL4_D2		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_TOP_SYSPLL4_D4		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_TOP_SYSPLL4_D16		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_TOP_UNIVPLL			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_TOP_UNIVPLL_D2		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_TOP_UNIVPLL1_D2		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_TOP_UNIVPLL1_D4		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_TOP_UNIVPLL1_D8		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_TOP_UNIVPLL1_D16		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_TOP_UNIVPLL2_D2		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_TOP_UNIVPLL2_D4		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_TOP_UNIVPLL2_D8		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CLK_TOP_UNIVPLL2_D16		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CLK_TOP_UNIVPLL_D5		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CLK_TOP_UNIVPLL3_D2		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_TOP_UNIVPLL3_D4		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CLK_TOP_UNIVPLL3_D16		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CLK_TOP_UNIVPLL_D7		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CLK_TOP_UNIVPLL_D80_D4		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLK_TOP_UNIV48M			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_TOP_SGMIIPLL		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_TOP_SGMIIPLL_D2		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_TOP_AUD1PLL			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_TOP_AUD2PLL			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_TOP_AUD_I2S2_MCK		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_TOP_TO_USB3_REF		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_TOP_PCIE1_MAC_EN		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLK_TOP_PCIE0_MAC_EN		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_TOP_ETH_500M		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_TOP_AXI_SEL			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_TOP_MEM_SEL			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_TOP_DDRPHYCFG_SEL		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_TOP_ETH_SEL			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLK_TOP_PWM_SEL			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_TOP_F10M_REF_SEL		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_TOP_NFI_INFRA_SEL		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_TOP_FLASH_SEL		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_TOP_UART_SEL		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_TOP_SPI0_SEL		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_TOP_SPI1_SEL		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_TOP_MSDC50_0_SEL		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_TOP_MSDC30_0_SEL		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLK_TOP_MSDC30_1_SEL		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CLK_TOP_A1SYS_HP_SEL		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_TOP_A2SYS_HP_SEL		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_TOP_INTDIR_SEL		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLK_TOP_AUD_INTBUS_SEL		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CLK_TOP_PMICSPI_SEL		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_TOP_SCP_SEL			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_TOP_ATB_SEL			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_TOP_HIF_SEL			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_TOP_AUDIO_SEL		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_TOP_U2_SEL			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_TOP_AUD1_SEL		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_TOP_AUD2_SEL		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CLK_TOP_IRRX_SEL		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_TOP_IRTX_SEL		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_TOP_ASM_L_SEL		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_TOP_ASM_M_SEL		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_TOP_ASM_H_SEL		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_TOP_APLL1_SEL		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_TOP_APLL2_SEL		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_TOP_I2S0_MCK_SEL		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_TOP_I2S1_MCK_SEL		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_TOP_I2S2_MCK_SEL		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_TOP_I2S3_MCK_SEL		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_TOP_APLL1_DIV		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_TOP_APLL2_DIV		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_TOP_I2S0_MCK_DIV		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_TOP_I2S1_MCK_DIV		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_TOP_I2S2_MCK_DIV		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_TOP_I2S3_MCK_DIV		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_TOP_A1SYS_HP_DIV		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_TOP_A2SYS_HP_DIV		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_TOP_APLL1_DIV_PD		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_TOP_APLL2_DIV_PD		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_TOP_I2S0_MCK_DIV_PD		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_TOP_I2S1_MCK_DIV_PD		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_TOP_I2S2_MCK_DIV_PD		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_TOP_I2S3_MCK_DIV_PD		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_TOP_A1SYS_HP_DIV_PD		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_TOP_A2SYS_HP_DIV_PD		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_TOP_NR_CLK			109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* INFRACFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_INFRA_MUX1_SEL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_INFRA_DBGCLK_PD		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_INFRA_AUDIO_PD		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_INFRA_IRRX_PD		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_INFRA_APXGPT_PD		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_INFRA_PMIC_PD		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_INFRA_TRNG			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_INFRA_NR_CLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* PERICFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_PERIBUS_SEL			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_PERI_THERM_PD		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_PERI_PWM1_PD		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_PERI_PWM2_PD		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_PERI_PWM3_PD		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_PERI_PWM4_PD		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_PERI_PWM5_PD		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_PERI_PWM6_PD		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_PERI_PWM7_PD		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_PERI_PWM_PD			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_PERI_AP_DMA_PD		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_PERI_MSDC30_0_PD		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_PERI_MSDC30_1_PD		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_PERI_UART0_PD		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_PERI_UART1_PD		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_PERI_UART2_PD		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_PERI_UART3_PD		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_PERI_UART4_PD		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_PERI_BTIF_PD		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_PERI_I2C0_PD		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_PERI_I2C1_PD		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_PERI_I2C2_PD		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_PERI_SPI1_PD		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_PERI_AUXADC_PD		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_PERI_SPI0_PD		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_PERI_SNFI_PD		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_PERI_NFI_PD			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_PERI_NFIECC_PD		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_PERI_FLASH_PD		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_PERI_IRTX_PD		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_PERI_NR_CLK			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* APMIXEDSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_APMIXED_ARMPLL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_APMIXED_MAINPLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_APMIXED_UNIV2PLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_APMIXED_ETH1PLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_APMIXED_ETH2PLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_APMIXED_AUD1PLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_APMIXED_AUD2PLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_APMIXED_TRGPLL		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_APMIXED_SGMIPLL		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_APMIXED_MAIN_CORE_EN	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_APMIXED_NR_CLK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* AUDIOSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_AUDIO_AFE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_AUDIO_HDMI			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_AUDIO_SPDF			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_AUDIO_APLL			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_AUDIO_I2SIN1		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_AUDIO_I2SIN2		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_AUDIO_I2SIN3		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_AUDIO_I2SIN4		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_AUDIO_I2SO1			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_AUDIO_I2SO2			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_AUDIO_I2SO3			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_AUDIO_I2SO4			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_AUDIO_ASRCI1		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_AUDIO_ASRCI2		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_AUDIO_ASRCO1		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_AUDIO_ASRCO2		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_AUDIO_INTDIR		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_AUDIO_A1SYS			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_AUDIO_A2SYS			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_AUDIO_UL1			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_AUDIO_UL2			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_AUDIO_UL3			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_AUDIO_UL4			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_AUDIO_UL5			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_AUDIO_UL6			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_AUDIO_DL1			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_AUDIO_DL2			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_AUDIO_DL3			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_AUDIO_DL4			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_AUDIO_DL5			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_AUDIO_DL6			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_AUDIO_DLMCH			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_AUDIO_ARB1			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_AUDIO_AWB			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_AUDIO_AWB2			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_AUDIO_DAI			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_AUDIO_MOD			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_AUDIO_ASRCI3		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_AUDIO_ASRCI4		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_AUDIO_ASRCO3		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_AUDIO_ASRCO4		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_AUDIO_MEM_ASRC1		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_AUDIO_MEM_ASRC2		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_AUDIO_MEM_ASRC3		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_AUDIO_MEM_ASRC4		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_AUDIO_MEM_ASRC5		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_AUDIO_AFE_CONN		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_AUDIO_NR_CLK		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* SSUSBSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_SSUSB_U2_PHY_1P_EN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_SSUSB_U2_PHY_EN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_SSUSB_REF_EN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_SSUSB_SYS_EN		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_SSUSB_MCU_EN		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_SSUSB_DMA_EN		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_SSUSB_NR_CLK		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* PCIESYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_PCIE_P1_AUX_EN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_PCIE_P1_OBFF_EN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_PCIE_P1_AHB_EN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_PCIE_P1_AXI_EN		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_PCIE_P1_MAC_EN		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_PCIE_P1_PIPE_EN		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_PCIE_P0_AUX_EN		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_PCIE_P0_OBFF_EN		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_PCIE_P0_AHB_EN		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CLK_PCIE_P0_AXI_EN		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_PCIE_P0_MAC_EN		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_PCIE_P0_PIPE_EN		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_SATA_AHB_EN			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_SATA_AXI_EN			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_SATA_ASIC_EN		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_SATA_RBC_EN			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_SATA_PM_EN			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_PCIE_NR_CLK			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* ETHSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_ETH_HSDMA_EN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK_ETH_ESW_EN			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_ETH_GP2_EN			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_ETH_GP1_EN			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_ETH_GP0_EN			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_ETH_NR_CLK			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* SGMIISYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_SGMII_TX250M_EN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_SGMII_RX250M_EN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_SGMII_CDR_REF		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_SGMII_CDR_FB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_SGMII_NR_CLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #endif /* _DT_BINDINGS_CLK_MT7622_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)