Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_MT6797_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_MT6797_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* TOPCKGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define	CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define	CLK_TOP_MUX_ULPOSC_AXI_CK_MUX		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define	CLK_TOP_MUX_AXI				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define	CLK_TOP_MUX_MEM				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define	CLK_TOP_MUX_DDRPHYCFG			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define	CLK_TOP_MUX_MM				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define	CLK_TOP_MUX_PWM				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define	CLK_TOP_MUX_VDEC			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define	CLK_TOP_MUX_VENC			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define	CLK_TOP_MUX_MFG				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define	CLK_TOP_MUX_CAMTG			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define	CLK_TOP_MUX_UART			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define	CLK_TOP_MUX_SPI				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define	CLK_TOP_MUX_ULPOSC_SPI_CK_MUX		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define	CLK_TOP_MUX_USB20			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define	CLK_TOP_MUX_MSDC50_0_HCLK		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define	CLK_TOP_MUX_MSDC50_0			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define	CLK_TOP_MUX_MSDC30_1			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define	CLK_TOP_MUX_MSDC30_2			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define	CLK_TOP_MUX_AUDIO			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define	CLK_TOP_MUX_AUD_INTBUS			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define	CLK_TOP_MUX_PMICSPI			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	CLK_TOP_MUX_SCP				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define	CLK_TOP_MUX_ATB				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define	CLK_TOP_MUX_MJC				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define	CLK_TOP_MUX_DPI0			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	CLK_TOP_MUX_AUD_1			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	CLK_TOP_MUX_AUD_2			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	CLK_TOP_MUX_SSUSB_TOP_SYS		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define	CLK_TOP_MUX_SPM				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define	CLK_TOP_MUX_BSI_SPI			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define	CLK_TOP_MUX_AUDIO_H			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	CLK_TOP_MUX_ANC_MD32			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define	CLK_TOP_MUX_MFG_52M			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define	CLK_TOP_SYSPLL_CK			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define	CLK_TOP_SYSPLL_D2			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define	CLK_TOP_SYSPLL1_D2			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define	CLK_TOP_SYSPLL1_D4			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define	CLK_TOP_SYSPLL1_D8			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define	CLK_TOP_SYSPLL1_D16			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define	CLK_TOP_SYSPLL_D3			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define	CLK_TOP_SYSPLL_D3_D3			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define	CLK_TOP_SYSPLL2_D2			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define	CLK_TOP_SYSPLL2_D4			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define	CLK_TOP_SYSPLL2_D8			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define	CLK_TOP_SYSPLL_D5			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define	CLK_TOP_SYSPLL3_D2			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define	CLK_TOP_SYSPLL3_D4			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define	CLK_TOP_SYSPLL_D7			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define	CLK_TOP_SYSPLL4_D2			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define	CLK_TOP_SYSPLL4_D4			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define	CLK_TOP_UNIVPLL_CK			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define	CLK_TOP_UNIVPLL_D7			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define	CLK_TOP_UNIVPLL_D26			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define	CLK_TOP_SSUSB_PHY_48M_CK		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define	CLK_TOP_USB_PHY48M_CK			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define	CLK_TOP_UNIVPLL_D2			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define	CLK_TOP_UNIVPLL1_D2			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define	CLK_TOP_UNIVPLL1_D4			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define	CLK_TOP_UNIVPLL1_D8			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define	CLK_TOP_UNIVPLL_D3			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define	CLK_TOP_UNIVPLL2_D2			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define	CLK_TOP_UNIVPLL2_D4			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define	CLK_TOP_UNIVPLL2_D8			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define	CLK_TOP_UNIVPLL_D5			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define	CLK_TOP_UNIVPLL3_D2			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define	CLK_TOP_UNIVPLL3_D4			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define	CLK_TOP_UNIVPLL3_D8			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define	CLK_TOP_ULPOSC_CK_ORG			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define	CLK_TOP_ULPOSC_CK			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define	CLK_TOP_ULPOSC_D2			71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define	CLK_TOP_ULPOSC_D3			72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define	CLK_TOP_ULPOSC_D4			73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define	CLK_TOP_ULPOSC_D8			74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define	CLK_TOP_ULPOSC_D10			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define	CLK_TOP_APLL1_CK			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define	CLK_TOP_APLL2_CK			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define	CLK_TOP_MFGPLL_CK			78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define	CLK_TOP_MFGPLL_D2			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define	CLK_TOP_IMGPLL_CK			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define	CLK_TOP_IMGPLL_D2			81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define	CLK_TOP_IMGPLL_D4			82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	CLK_TOP_CODECPLL_CK			83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define	CLK_TOP_CODECPLL_D2			84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define	CLK_TOP_VDECPLL_CK			85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define	CLK_TOP_TVDPLL_CK			86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define	CLK_TOP_TVDPLL_D2			87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define	CLK_TOP_TVDPLL_D4			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define	CLK_TOP_TVDPLL_D8			89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define	CLK_TOP_TVDPLL_D16			90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define	CLK_TOP_MSDCPLL_CK			91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define	CLK_TOP_MSDCPLL_D2			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define	CLK_TOP_MSDCPLL_D4			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define	CLK_TOP_MSDCPLL_D8			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define	CLK_TOP_NR				95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* APMIXED_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_APMIXED_MAINPLL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_APMIXED_UNIVPLL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_APMIXED_MFGPLL			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_APMIXED_MSDCPLL			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_APMIXED_IMGPLL			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_APMIXED_TVDPLL			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_APMIXED_CODECPLL			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_APMIXED_VDECPLL			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_APMIXED_APLL1			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_APMIXED_APLL2			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_APMIXED_NR				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* INFRA_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define	CLK_INFRA_PMIC_TMR			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define	CLK_INFRA_PMIC_AP			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define	CLK_INFRA_PMIC_MD			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define	CLK_INFRA_PMIC_CONN			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define	CLK_INFRA_SCP				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define	CLK_INFRA_SEJ				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define	CLK_INFRA_APXGPT			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define	CLK_INFRA_SEJ_13M			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define	CLK_INFRA_ICUSB				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define	CLK_INFRA_GCE				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define	CLK_INFRA_THERM				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define	CLK_INFRA_I2C0				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define	CLK_INFRA_I2C1				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define	CLK_INFRA_I2C2				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define	CLK_INFRA_I2C3				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define	CLK_INFRA_PWM_HCLK			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define	CLK_INFRA_PWM1				17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define	CLK_INFRA_PWM2				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define	CLK_INFRA_PWM3				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define	CLK_INFRA_PWM4				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define	CLK_INFRA_PWM				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define	CLK_INFRA_UART0				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define	CLK_INFRA_UART1				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define	CLK_INFRA_UART2				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define	CLK_INFRA_UART3				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define	CLK_INFRA_MD2MD_CCIF_0			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define	CLK_INFRA_MD2MD_CCIF_1			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define	CLK_INFRA_MD2MD_CCIF_2			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define	CLK_INFRA_FHCTL				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define	CLK_INFRA_BTIF				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define	CLK_INFRA_MD2MD_CCIF_3			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define	CLK_INFRA_SPI				32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define	CLK_INFRA_MSDC0				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define	CLK_INFRA_MD2MD_CCIF_4			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define	CLK_INFRA_MSDC1				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define	CLK_INFRA_MSDC2				36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define	CLK_INFRA_MD2MD_CCIF_5			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define	CLK_INFRA_GCPU				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define	CLK_INFRA_TRNG				39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define	CLK_INFRA_AUXADC			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define	CLK_INFRA_CPUM				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define	CLK_INFRA_AP_C2K_CCIF_0			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define	CLK_INFRA_AP_C2K_CCIF_1			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define	CLK_INFRA_CLDMA				44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define	CLK_INFRA_DISP_PWM			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define	CLK_INFRA_AP_DMA			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define	CLK_INFRA_DEVICE_APC			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define	CLK_INFRA_L2C_SRAM			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define	CLK_INFRA_CCIF_AP			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define	CLK_INFRA_AUDIO				50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define	CLK_INFRA_CCIF_MD			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define	CLK_INFRA_DRAMC_F26M			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define	CLK_INFRA_I2C4				53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define	CLK_INFRA_I2C_APPM			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define	CLK_INFRA_I2C_GPUPM			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define	CLK_INFRA_I2C2_IMM			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define	CLK_INFRA_I2C2_ARB			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define	CLK_INFRA_I2C3_IMM			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define	CLK_INFRA_I2C3_ARB			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define	CLK_INFRA_I2C5				60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define	CLK_INFRA_SYS_CIRQ			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define	CLK_INFRA_SPI1				62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define	CLK_INFRA_DRAMC_B_F26M			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define	CLK_INFRA_ANC_MD32			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define	CLK_INFRA_ANC_MD32_32K			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define	CLK_INFRA_DVFS_SPM1			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define	CLK_INFRA_AES_TOP0			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define	CLK_INFRA_AES_TOP1			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define	CLK_INFRA_SSUSB_BUS			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define	CLK_INFRA_SPI2				70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define	CLK_INFRA_SPI3				71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define	CLK_INFRA_SPI4				72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define	CLK_INFRA_SPI5				73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define	CLK_INFRA_IRTX				74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define	CLK_INFRA_SSUSB_SYS			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define	CLK_INFRA_SSUSB_REF			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define	CLK_INFRA_AUDIO_26M			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define	CLK_INFRA_AUDIO_26M_PAD_TOP		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define	CLK_INFRA_MODEM_TEMP_SHARE		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define	CLK_INFRA_VAD_WRAP_SOC			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define	CLK_INFRA_DRAMC_CONF			81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define	CLK_INFRA_DRAMC_B_CONF			82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define	CLK_INFRA_MFG_VCG			83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define	CLK_INFRA_13M				84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define	CLK_INFRA_NR				85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* IMG_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define	CLK_IMG_FDVT				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define	CLK_IMG_DPE				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define	CLK_IMG_DIP				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define	CLK_IMG_LARB6				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define	CLK_IMG_NR				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* MM_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define	CLK_MM_SMI_COMMON			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define	CLK_MM_SMI_LARB0			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define	CLK_MM_SMI_LARB5			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define	CLK_MM_CAM_MDP				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define	CLK_MM_MDP_RDMA0			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define	CLK_MM_MDP_RDMA1			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define	CLK_MM_MDP_RSZ0				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define	CLK_MM_MDP_RSZ1				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define	CLK_MM_MDP_RSZ2				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define	CLK_MM_MDP_TDSHP			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define	CLK_MM_MDP_COLOR			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define	CLK_MM_MDP_WDMA				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define	CLK_MM_MDP_WROT0			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define	CLK_MM_MDP_WROT1			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define	CLK_MM_FAKE_ENG				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define	CLK_MM_DISP_OVL0			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define	CLK_MM_DISP_OVL1			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define	CLK_MM_DISP_OVL0_2L			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define	CLK_MM_DISP_OVL1_2L			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define	CLK_MM_DISP_RDMA0			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define	CLK_MM_DISP_RDMA1			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define	CLK_MM_DISP_WDMA0			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define	CLK_MM_DISP_WDMA1			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define	CLK_MM_DISP_COLOR			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define	CLK_MM_DISP_CCORR			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define	CLK_MM_DISP_AAL				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define	CLK_MM_DISP_GAMMA			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define	CLK_MM_DISP_OD				28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define	CLK_MM_DISP_DITHER			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define	CLK_MM_DISP_UFOE			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define	CLK_MM_DISP_DSC				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define	CLK_MM_DISP_SPLIT			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define	CLK_MM_DSI0_MM_CLOCK			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define	CLK_MM_DSI1_MM_CLOCK			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define	CLK_MM_DPI_MM_CLOCK			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define	CLK_MM_DPI_INTERFACE_CLOCK		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define	CLK_MM_LARB4_AXI_ASIF_MM_CLOCK		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define	CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define	CLK_MM_DISP_OVL0_MOUT_CLOCK		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define	CLK_MM_FAKE_ENG2			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define	CLK_MM_DSI0_INTERFACE_CLOCK		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define	CLK_MM_DSI1_INTERFACE_CLOCK		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define	CLK_MM_NR				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* VDEC_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define	CLK_VDEC_CKEN_ENG			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define	CLK_VDEC_ACTIVE				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define	CLK_VDEC_CKEN				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define	CLK_VDEC_LARB1_CKEN			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define	CLK_VDEC_NR				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* VENC_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define	CLK_VENC_0				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define	CLK_VENC_1				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define	CLK_VENC_2				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define	CLK_VENC_3				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define	CLK_VENC_NR				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #endif /* _DT_BINDINGS_CLK_MT6797_H */