Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Wendell Lin <wendell.lin@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_MT6779_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_MT6779_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* TOPCKGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define CLK_TOP_AXI			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CLK_TOP_MM			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CLK_TOP_CAM			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CLK_TOP_MFG			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CLK_TOP_CAMTG			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CLK_TOP_UART			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CLK_TOP_SPI			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CLK_TOP_MSDC50_0_HCLK		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLK_TOP_MSDC50_0		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CLK_TOP_MSDC30_1		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CLK_TOP_MSDC30_2		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CLK_TOP_AUD			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLK_TOP_AUD_INTBUS		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLK_TOP_FPWRAP_ULPOSC		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_TOP_SCP			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_TOP_ATB			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_TOP_SSPM			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLK_TOP_DPI0			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_TOP_SCAM			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLK_TOP_AUD_1			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_TOP_AUD_2			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLK_TOP_DISP_PWM		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CLK_TOP_SSUSB_TOP_XHCI		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CLK_TOP_USB_TOP			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CLK_TOP_SPM			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_TOP_I2C			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_TOP_F52M_MFG		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_TOP_SENINF			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_TOP_DXCC			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_TOP_CAMTG2			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_TOP_AUD_ENG1		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_TOP_AUD_ENG2		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_TOP_FAES_UFSFDE		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_TOP_FUFS			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_TOP_IMG			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_TOP_DSP			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_TOP_DSP1			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_TOP_DSP2			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_TOP_IPU_IF			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_TOP_CAMTG3			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CLK_TOP_CAMTG4			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CLK_TOP_PMICSPI			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CLK_TOP_MAINPLL_CK		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_TOP_MAINPLL_D2		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CLK_TOP_MAINPLL_D3		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CLK_TOP_MAINPLL_D5		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CLK_TOP_MAINPLL_D7		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLK_TOP_MAINPLL_D2_D2		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_TOP_MAINPLL_D2_D4		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_TOP_MAINPLL_D2_D8		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_TOP_MAINPLL_D2_D16		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_TOP_MAINPLL_D3_D2		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_TOP_MAINPLL_D3_D4		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_TOP_MAINPLL_D3_D8		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_TOP_MAINPLL_D5_D2		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLK_TOP_MAINPLL_D5_D4		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_TOP_MAINPLL_D7_D2		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_TOP_MAINPLL_D7_D4		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_TOP_UNIVPLL_CK		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_TOP_UNIVPLL_D2		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_TOP_UNIVPLL_D3		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLK_TOP_UNIVPLL_D5		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_TOP_UNIVPLL_D7		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_TOP_UNIVPLL_D2_D2		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_TOP_UNIVPLL_D2_D4		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_TOP_UNIVPLL_D2_D8		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_TOP_UNIVPLL_D3_D2		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_TOP_UNIVPLL_D3_D4		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_TOP_UNIVPLL_D3_D8		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_TOP_UNIVPLL_D5_D2		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLK_TOP_UNIVPLL_D5_D4		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CLK_TOP_UNIVPLL_D5_D8		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_TOP_APLL1_CK		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_TOP_APLL1_D2		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLK_TOP_APLL1_D4		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CLK_TOP_APLL1_D8		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_TOP_APLL2_CK		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_TOP_APLL2_D2		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_TOP_APLL2_D4		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_TOP_APLL2_D8		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_TOP_TVDPLL_CK		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_TOP_TVDPLL_D2		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_TOP_TVDPLL_D4		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CLK_TOP_TVDPLL_D8		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_TOP_TVDPLL_D16		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_TOP_MSDCPLL_CK		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_TOP_MSDCPLL_D2		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_TOP_MSDCPLL_D4		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_TOP_MSDCPLL_D8		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_TOP_MSDCPLL_D16		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_TOP_AD_OSC_CK		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_TOP_OSC_D2			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_TOP_OSC_D4			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_TOP_OSC_D8			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_TOP_OSC_D16			95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_TOP_F26M_CK_D2		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_TOP_MFGPLL_CK		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_TOP_UNIVP_192M_CK		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_TOP_UNIVP_192M_D2		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_TOP_UNIVP_192M_D4		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_TOP_UNIVP_192M_D8		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_TOP_UNIVP_192M_D16		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_TOP_UNIVP_192M_D32		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_TOP_MMPLL_CK		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_TOP_MMPLL_D4		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_TOP_MMPLL_D4_D2		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_TOP_MMPLL_D4_D4		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_TOP_MMPLL_D5		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_TOP_MMPLL_D5_D2		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_TOP_MMPLL_D5_D4		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_TOP_MMPLL_D6		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_TOP_MMPLL_D7		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_TOP_CLK26M			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_TOP_CLK13M			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_TOP_ADSP			115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_TOP_DPMAIF			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_TOP_VENC			117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_TOP_VDEC			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_TOP_CAMTM			119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_TOP_PWM			120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_TOP_ADSPPLL_CK		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_TOP_I2S0_M_SEL		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_TOP_I2S1_M_SEL		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_TOP_I2S2_M_SEL		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_TOP_I2S3_M_SEL		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_TOP_I2S4_M_SEL		126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_TOP_I2S5_M_SEL		127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_TOP_APLL12_DIV0		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_TOP_APLL12_DIV1		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_TOP_APLL12_DIV2		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_TOP_APLL12_DIV3		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_TOP_APLL12_DIV4		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_TOP_APLL12_DIVB		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_TOP_APLL12_DIV5		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_TOP_IPE			135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_TOP_DPE			136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_TOP_CCU			137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_TOP_DSP3			138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_TOP_SENINF1			139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_TOP_SENINF2			140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_TOP_AUD_H			141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_TOP_CAMTG5			142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_TOP_TVDPLL_MAINPLL_D2_CK	143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_TOP_AD_OSC2_CK		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_TOP_OSC2_D2			145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_TOP_OSC2_D3			146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_TOP_FMEM_466M_CK		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_TOP_ADSPPLL_D4		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_TOP_ADSPPLL_D5		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_TOP_ADSPPLL_D6		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_TOP_OSC_D10			151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_TOP_UNIVPLL_D3_D16		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_TOP_NR_CLK			153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* APMIXED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_APMIXED_ARMPLL_LL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_APMIXED_ARMPLL_BL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_APMIXED_ARMPLL_BB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_APMIXED_CCIPLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_APMIXED_MAINPLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_APMIXED_UNIV2PLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_APMIXED_MSDCPLL		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_APMIXED_ADSPPLL		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_APMIXED_MMPLL		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_APMIXED_MFGPLL		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_APMIXED_TVDPLL		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_APMIXED_APLL1		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_APMIXED_APLL2		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_APMIXED_SSUSB26M		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_APMIXED_APPLL26M		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_APMIXED_MIPIC0_26M		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_APMIXED_MDPLLGP26M		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_APMIXED_MM_F26M		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_APMIXED_UFS26M		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_APMIXED_MIPIC1_26M		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_APMIXED_MEMPLL26M		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_APMIXED_CLKSQ_LVPLL_26M	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_APMIXED_MIPID0_26M		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_APMIXED_MIPID1_26M		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_APMIXED_NR_CLK		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* CAMSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_CAM_LARB10			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_CAM_DFP_VAD			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_CAM_LARB11			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_CAM_LARB9			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_CAM_CAM			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_CAM_CAMTG			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_CAM_SENINF			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_CAM_CAMSV0			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_CAM_CAMSV1			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_CAM_CAMSV2			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_CAM_CAMSV3			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_CAM_CCU			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_CAM_FAKE_ENG		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_CAM_NR_CLK			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* INFRA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_INFRA_PMIC_TMR		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_INFRA_PMIC_AP		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_INFRA_PMIC_MD		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_INFRA_PMIC_CONN		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_INFRA_SCPSYS		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_INFRA_SEJ			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_INFRA_APXGPT		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_INFRA_ICUSB			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_INFRA_GCE			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_INFRA_THERM			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_INFRA_I2C0			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_INFRA_I2C1			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_INFRA_I2C2			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_INFRA_I2C3			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_INFRA_PWM_HCLK		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_INFRA_PWM1			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_INFRA_PWM2			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_INFRA_PWM3			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_INFRA_PWM4			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_INFRA_PWM			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_INFRA_UART0			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_INFRA_UART1			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_INFRA_UART2			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_INFRA_UART3			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_INFRA_GCE_26M		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_INFRA_CQ_DMA_FPC		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_INFRA_BTIF			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_INFRA_SPI0			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_INFRA_MSDC0			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_INFRA_MSDC1			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_INFRA_MSDC2			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_INFRA_MSDC0_SCK		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_INFRA_DVFSRC		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_INFRA_GCPU			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLK_INFRA_TRNG			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLK_INFRA_AUXADC		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_INFRA_CPUM			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_INFRA_CCIF1_AP		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_INFRA_CCIF1_MD		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_INFRA_AUXADC_MD		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_INFRA_MSDC1_SCK		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_INFRA_MSDC2_SCK		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_INFRA_AP_DMA		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_INFRA_XIU			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_INFRA_DEVICE_APC		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CLK_INFRA_CCIF_AP		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_INFRA_DEBUGSYS		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_INFRA_AUD			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_INFRA_CCIF_MD		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_INFRA_DXCC_SEC_CORE		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_INFRA_DXCC_AO		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_INFRA_DRAMC_F26M		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_INFRA_IRTX			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_INFRA_DISP_PWM		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_INFRA_DPMAIF_CK		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLK_INFRA_AUD_26M_BCLK		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLK_INFRA_SPI1			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_INFRA_I2C4			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK_INFRA_MODEM_TEMP_SHARE	59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_INFRA_SPI2			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_INFRA_SPI3			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_INFRA_UNIPRO_SCK		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_INFRA_UNIPRO_TICK		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLK_INFRA_UFS_MP_SAP_BCLK	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_INFRA_MD32_BCLK		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLK_INFRA_SSPM			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_INFRA_UNIPRO_MBIST		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_INFRA_SSPM_BUS_HCLK		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_INFRA_I2C5			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_INFRA_I2C5_ARBITER		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_INFRA_I2C5_IMM		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CLK_INFRA_I2C1_ARBITER		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_INFRA_I2C1_IMM		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CLK_INFRA_I2C2_ARBITER		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CLK_INFRA_I2C2_IMM		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CLK_INFRA_SPI4			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CLK_INFRA_SPI5			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CLK_INFRA_CQ_DMA		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CLK_INFRA_UFS			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CLK_INFRA_AES_UFSFDE		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CLK_INFRA_UFS_TICK		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CLK_INFRA_MSDC0_SELF		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CLK_INFRA_MSDC1_SELF		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CLK_INFRA_MSDC2_SELF		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CLK_INFRA_SSPM_26M_SELF		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CLK_INFRA_SSPM_32K_SELF		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CLK_INFRA_UFS_AXI		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CLK_INFRA_I2C6			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CLK_INFRA_AP_MSDC0		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CLK_INFRA_MD_MSDC0		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CLK_INFRA_USB			91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CLK_INFRA_DEVMPU_BCLK		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CLK_INFRA_CCIF2_AP		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CLK_INFRA_CCIF2_MD		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CLK_INFRA_CCIF3_AP		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CLK_INFRA_CCIF3_MD		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CLK_INFRA_SEJ_F13M		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CLK_INFRA_AES_BCLK		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CLK_INFRA_I2C7			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLK_INFRA_I2C8			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CLK_INFRA_FBIST2FPC		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CLK_INFRA_CCIF4_AP		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CLK_INFRA_CCIF4_MD		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CLK_INFRA_FADSP			104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CLK_INFRA_SSUSB_XHCI		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CLK_INFRA_SPI6			106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CLK_INFRA_SPI7			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CLK_INFRA_NR_CLK		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* MFGCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CLK_MFGCFG_BG3D			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CLK_MFGCFG_NR_CLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* IMG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CLK_IMG_WPE_A			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLK_IMG_MFB			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CLK_IMG_DIP			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CLK_IMG_LARB6			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CLK_IMG_LARB5			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CLK_IMG_NR_CLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* IPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CLK_IPE_LARB7			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CLK_IPE_LARB8			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CLK_IPE_SMI_SUBCOM		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CLK_IPE_FD			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CLK_IPE_FE			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CLK_IPE_RSC			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CLK_IPE_DPE			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CLK_IPE_NR_CLK			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* MM_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CLK_MM_SMI_COMMON		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CLK_MM_SMI_LARB0		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CLK_MM_SMI_LARB1		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CLK_MM_GALS_COMM0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CLK_MM_GALS_COMM1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CLK_MM_GALS_CCU2MM		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define CLK_MM_GALS_IPU12MM		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CLK_MM_GALS_IMG2MM		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CLK_MM_GALS_CAM2MM		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define CLK_MM_GALS_IPU2MM		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define CLK_MM_MDP_DL_TXCK		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CLK_MM_IPU_DL_TXCK		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CLK_MM_MDP_RDMA0		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CLK_MM_MDP_RDMA1		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CLK_MM_MDP_RSZ0			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CLK_MM_MDP_RSZ1			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CLK_MM_MDP_TDSHP		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CLK_MM_MDP_WROT0		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CLK_MM_FAKE_ENG			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CLK_MM_DISP_OVL0		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CLK_MM_DISP_OVL0_2L		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define CLK_MM_DISP_OVL1_2L		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CLK_MM_DISP_RDMA0		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CLK_MM_DISP_RDMA1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define CLK_MM_DISP_WDMA0		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CLK_MM_DISP_COLOR0		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CLK_MM_DISP_CCORR0		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CLK_MM_DISP_AAL0		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CLK_MM_DISP_GAMMA0		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CLK_MM_DISP_DITHER0		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define CLK_MM_DISP_SPLIT		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CLK_MM_DSI0_MM_CK		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CLK_MM_DSI0_IF_CK		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CLK_MM_DPI_MM_CK		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CLK_MM_DPI_IF_CK		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CLK_MM_FAKE_ENG2		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CLK_MM_MDP_DL_RX_CK		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CLK_MM_IPU_DL_RX_CK		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CLK_MM_26M			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CLK_MM_MM_R2Y			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CLK_MM_DISP_RSZ			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CLK_MM_MDP_WDMA0		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CLK_MM_MDP_AAL			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CLK_MM_MDP_HDR			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CLK_MM_DBI_MM_CK		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CLK_MM_DBI_IF_CK		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define CLK_MM_MDP_WROT1		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CLK_MM_DISP_POSTMASK0		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CLK_MM_DISP_HRT_BW		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CLK_MM_DISP_OVL_FBDC		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CLK_MM_NR_CLK			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* VDEC_GCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CLK_VDEC_VDEC			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CLK_VDEC_LARB1			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CLK_VDEC_GCON_NR_CLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* VENC_GCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CLK_VENC_GCON_LARB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CLK_VENC_GCON_VENC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define CLK_VENC_GCON_JPGENC		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define CLK_VENC_GCON_GALS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CLK_VENC_GCON_NR_CLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* AUD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define CLK_AUD_AFE			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define CLK_AUD_22M			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CLK_AUD_24M			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CLK_AUD_APLL2_TUNER		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CLK_AUD_APLL_TUNER		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CLK_AUD_TDM			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CLK_AUD_ADC			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CLK_AUD_DAC			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CLK_AUD_DAC_PREDIS		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CLK_AUD_TML			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CLK_AUD_NLE			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define CLK_AUD_I2S1_BCLK_SW		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define CLK_AUD_I2S2_BCLK_SW		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define CLK_AUD_I2S3_BCLK_SW		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define CLK_AUD_I2S4_BCLK_SW		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CLK_AUD_I2S5_BCLK_SW		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CLK_AUD_CONN_I2S_ASRC		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define CLK_AUD_GENERAL1_ASRC		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CLK_AUD_GENERAL2_ASRC		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CLK_AUD_DAC_HIRES		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CLK_AUD_PDN_ADDA6_ADC		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define CLK_AUD_ADC_HIRES		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CLK_AUD_ADC_HIRES_TML		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CLK_AUD_ADDA6_ADC_HIRES		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CLK_AUD_3RD_DAC			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CLK_AUD_3RD_DAC_PREDIS		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CLK_AUD_3RD_DAC_TML		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CLK_AUD_3RD_DAC_HIRES		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CLK_AUD_NR_CLK			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #endif /* _DT_BINDINGS_CLK_MT6779_H */