Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #ifndef _DT_BINDINGS_CLK_MT6765_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #define _DT_BINDINGS_CLK_MT6765_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) /* FIX Clks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define CLK_TOP_CLK26M			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /* APMIXEDSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define CLK_APMIXED_ARMPLL_L		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define CLK_APMIXED_ARMPLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CLK_APMIXED_CCIPLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CLK_APMIXED_MAINPLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CLK_APMIXED_MFGPLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CLK_APMIXED_MMPLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CLK_APMIXED_UNIV2PLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CLK_APMIXED_MSDCPLL		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CLK_APMIXED_APLL1		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLK_APMIXED_MPLL		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CLK_APMIXED_ULPOSC1		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CLK_APMIXED_ULPOSC2		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CLK_APMIXED_SSUSB26M		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLK_APMIXED_APPLL26M		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLK_APMIXED_MIPIC0_26M		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_APMIXED_MDPLLGP26M		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_APMIXED_MMSYS_F26M		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_APMIXED_UFS26M		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLK_APMIXED_MIPIC1_26M		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_APMIXED_MEMPLL26M		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLK_APMIXED_CLKSQ_LVPLL_26M	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_APMIXED_MIPID0_26M		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLK_APMIXED_NR_CLK		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* TOPCKGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CLK_TOP_SYSPLL			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_TOP_SYSPLL_D2		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_TOP_SYSPLL1_D2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_TOP_SYSPLL1_D4		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_TOP_SYSPLL1_D8		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_TOP_SYSPLL1_D16		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_TOP_SYSPLL_D3		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_TOP_SYSPLL2_D2		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_TOP_SYSPLL2_D4		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_TOP_SYSPLL2_D8		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_TOP_SYSPLL_D5		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_TOP_SYSPLL3_D2		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_TOP_SYSPLL3_D4		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_TOP_SYSPLL_D7		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_TOP_SYSPLL4_D2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_TOP_SYSPLL4_D4		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CLK_TOP_USB20_192M		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CLK_TOP_USB20_192M_D4		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CLK_TOP_USB20_192M_D8		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_TOP_USB20_192M_D16		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CLK_TOP_USB20_192M_D32		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CLK_TOP_UNIVPLL			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CLK_TOP_UNIVPLL_D2		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLK_TOP_UNIVPLL1_D2		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_TOP_UNIVPLL1_D4		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_TOP_UNIVPLL_D3		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_TOP_UNIVPLL2_D2		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_TOP_UNIVPLL2_D4		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_TOP_UNIVPLL2_D8		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_TOP_UNIVPLL2_D32		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_TOP_UNIVPLL_D5		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLK_TOP_UNIVPLL3_D2		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_TOP_UNIVPLL3_D4		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_TOP_MMPLL			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_TOP_MMPLL_D2		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_TOP_MPLL			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_TOP_DA_MPLL_104M_DIV	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLK_TOP_DA_MPLL_52M_DIV		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_TOP_MFGPLL			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_TOP_MSDCPLL			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_TOP_MSDCPLL_D2		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_TOP_APLL1			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_TOP_APLL1_D2		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_TOP_APLL1_D4		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_TOP_APLL1_D8		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_TOP_ULPOSC1			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLK_TOP_ULPOSC1_D2		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CLK_TOP_ULPOSC1_D4		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_TOP_ULPOSC1_D8		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_TOP_ULPOSC1_D16		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLK_TOP_ULPOSC1_D32		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CLK_TOP_DMPLL			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_TOP_F_FRTC			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_TOP_F_F26M			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_TOP_AXI			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_TOP_MM			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_TOP_SCP			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_TOP_MFG			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_TOP_F_FUART			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CLK_TOP_SPI			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_TOP_MSDC50_0		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_TOP_MSDC30_1		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_TOP_AUDIO			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_TOP_AUD_1			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_TOP_AUD_ENGEN1		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_TOP_F_FDISP_PWM		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_TOP_SSPM			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_TOP_DXCC			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_TOP_I2C			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_TOP_F_FPWM			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_TOP_F_FSENINF		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_TOP_AES_FDE			71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_TOP_F_BIST2FPC		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_TOP_ARMPLL_DIVIDER_PLL0	73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_TOP_ARMPLL_DIVIDER_PLL1	74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_TOP_ARMPLL_DIVIDER_PLL2	75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_TOP_DA_USB20_48M_DIV	76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_TOP_DA_UNIV_48M_DIV		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_TOP_APLL12_DIV0		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_TOP_APLL12_DIV1		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_TOP_APLL12_DIV2		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_TOP_APLL12_DIV3		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN	82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN	83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN	84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_TOP_FMEM_OCC_DRC_EN		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_TOP_USB20_48M_EN		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_TOP_UNIVPLL_48M_EN		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_TOP_MPLL_104M_EN		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_TOP_MPLL_52M_EN		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_TOP_F_UFS_MP_SAP_CFG_EN	90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_TOP_F_BIST2FPC_EN		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_TOP_MD_32K			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_TOP_MD_26M			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_TOP_MD2_32K			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_TOP_MD2_26M			95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_TOP_AXI_SEL			96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_TOP_MEM_SEL			97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_TOP_MM_SEL			98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_TOP_SCP_SEL			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_TOP_MFG_SEL			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_TOP_ATB_SEL			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_TOP_CAMTG_SEL		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_TOP_CAMTG1_SEL		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_TOP_CAMTG2_SEL		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_TOP_CAMTG3_SEL		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_TOP_UART_SEL		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_TOP_SPI_SEL			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_TOP_MSDC50_0_HCLK_SEL	108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_TOP_MSDC50_0_SEL		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_TOP_MSDC30_1_SEL		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_TOP_AUDIO_SEL		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_TOP_AUD_INTBUS_SEL		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_TOP_AUD_1_SEL		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_TOP_AUD_ENGEN1_SEL		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_TOP_DISP_PWM_SEL		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_TOP_SSPM_SEL		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_TOP_DXCC_SEL		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_TOP_USB_TOP_SEL		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_TOP_SPM_SEL			119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_TOP_I2C_SEL			120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_TOP_PWM_SEL			121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_TOP_SENINF_SEL		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_TOP_AES_FDE_SEL		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_TOP_PWRAP_ULPOSC_SEL	124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_TOP_CAMTM_SEL		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_TOP_NR_CLK			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* INFRACFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_IFR_ICUSB			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_IFR_GCE			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_IFR_THERM			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_IFR_I2C_AP			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_IFR_I2C_CCU			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_IFR_I2C_SSPM		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_IFR_I2C_RSV			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_IFR_PWM_HCLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_IFR_PWM1			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_IFR_PWM2			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_IFR_PWM3			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_IFR_PWM4			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_IFR_PWM5			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_IFR_PWM			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_IFR_UART0			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_IFR_UART1			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_IFR_GCE_26M			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_IFR_CQ_DMA_FPC		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_IFR_BTIF			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_IFR_SPI0			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_IFR_MSDC0			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_IFR_MSDC1			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_IFR_TRNG			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_IFR_AUXADC			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_IFR_CCIF1_AP		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_IFR_CCIF1_MD		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_IFR_AUXADC_MD		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_IFR_AP_DMA			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_IFR_DEVICE_APC		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_IFR_CCIF_AP			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_IFR_AUDIO			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_IFR_CCIF_MD			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_IFR_RG_PWM_FBCLK6		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_IFR_DISP_PWM		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_IFR_CLDMA_BCLK		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_IFR_AUDIO_26M_BCLK		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_IFR_SPI1			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_IFR_I2C4			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_IFR_SPI2			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_IFR_SPI3			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_IFR_I2C5			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_IFR_I2C5_ARBITER		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_IFR_I2C5_IMM		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_IFR_I2C1_ARBITER		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_IFR_I2C1_IMM		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_IFR_I2C2_ARBITER		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_IFR_I2C2_IMM		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_IFR_SPI4			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_IFR_SPI5			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_IFR_CQ_DMA			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_IFR_FAES_FDE		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_IFR_MSDC0_SELF		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_IFR_MSDC1_SELF		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_IFR_I2C6			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_IFR_AP_MSDC0		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_IFR_MD_MSDC0		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_IFR_MSDC0_SRC		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_IFR_MSDC1_SRC		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_IFR_AES_TOP0_BCLK		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_IFR_MCU_PM_BCLK		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_IFR_CCIF2_AP		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_IFR_CCIF2_MD		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_IFR_CCIF3_AP		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_IFR_CCIF3_MD		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_IFR_NR_CLK			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* AUDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_AUDIO_AFE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_AUDIO_22M			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_AUDIO_APLL_TUNER		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_AUDIO_ADC			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_AUDIO_DAC			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_AUDIO_DAC_PREDIS		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_AUDIO_TML			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_AUDIO_I2S1_BCLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_AUDIO_I2S2_BCLK		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_AUDIO_I2S3_BCLK		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_AUDIO_I2S4_BCLK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_AUDIO_NR_CLK		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* MIPI_RX_ANA_CSI0A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_MIPI0A_CSR_CSI_EN_0A	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_MIPI0A_NR_CLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* MMSYS_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_MM_MDP_RDMA0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_MM_MDP_CCORR0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_MM_MDP_RSZ0			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CLK_MM_MDP_RSZ1			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_MM_MDP_TDSHP0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_MM_MDP_WROT0		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_MM_MDP_WDMA0		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_MM_DISP_OVL0		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_MM_DISP_OVL0_2L		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_MM_DISP_RSZ0		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_MM_DISP_RDMA0		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_MM_DISP_WDMA0		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_MM_DISP_COLOR0		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLK_MM_DISP_CCORR0		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLK_MM_DISP_AAL0		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_MM_DISP_GAMMA0		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK_MM_DISP_DITHER0		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_MM_DSI0			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_MM_FAKE_ENG			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_MM_SMI_COMMON		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_MM_SMI_LARB0		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLK_MM_SMI_COMM0		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_MM_SMI_COMM1		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLK_MM_CAM_MDP			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_MM_SMI_IMG			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_MM_SMI_CAM			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_MM_IMG_DL_RELAY		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_MM_IMG_DL_ASYNC_TOP		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_MM_DIG_DSI			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CLK_MM_F26M_HRTWT		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_MM_NR_CLK			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* IMGSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CLK_IMG_LARB2			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CLK_IMG_DIP			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CLK_IMG_FDVT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CLK_IMG_DPE			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CLK_IMG_RSC			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CLK_IMG_NR_CLK			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* VENCSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CLK_VENC_SET0_LARB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CLK_VENC_SET1_VENC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CLK_VENC_SET2_JPGENC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CLK_VENC_SET3_VDEC		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CLK_VENC_NR_CLK			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* CAMSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CLK_CAM_LARB3			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CLK_CAM_DFP_VAD			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CLK_CAM				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CLK_CAMTG			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CLK_CAM_SENINF			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CLK_CAMSV0			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLK_CAMSV1			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CLK_CAMSV2			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CLK_CAM_CCU			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CLK_CAM_NR_CLK			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #endif /* _DT_BINDINGS_CLK_MT6765_H */