Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_MT2712_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_MT2712_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* APMIXEDSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CLK_APMIXED_MAINPLL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CLK_APMIXED_UNIVPLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CLK_APMIXED_VCODECPLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CLK_APMIXED_VENCPLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CLK_APMIXED_APLL1		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CLK_APMIXED_APLL2		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CLK_APMIXED_LVDSPLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLK_APMIXED_LVDSPLL2		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CLK_APMIXED_MSDCPLL		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CLK_APMIXED_MSDCPLL2		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CLK_APMIXED_TVDPLL		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLK_APMIXED_MMPLL		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLK_APMIXED_ARMCA35PLL		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_APMIXED_ARMCA72PLL		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_APMIXED_ETHERPLL		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_APMIXED_NR_CLK		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* TOPCKGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_TOP_ARMCA35PLL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLK_TOP_ARMCA35PLL_600M		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CLK_TOP_ARMCA35PLL_400M		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CLK_TOP_ARMCA72PLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CLK_TOP_SYSPLL			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_TOP_SYSPLL_D2		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_TOP_SYSPLL1_D2		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_TOP_SYSPLL1_D4		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_TOP_SYSPLL1_D8		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_TOP_SYSPLL1_D16		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_TOP_SYSPLL_D3		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_TOP_SYSPLL2_D2		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_TOP_SYSPLL2_D4		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_TOP_SYSPLL_D5		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_TOP_SYSPLL3_D2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_TOP_SYSPLL3_D4		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_TOP_SYSPLL_D7		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_TOP_SYSPLL4_D2		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_TOP_SYSPLL4_D4		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_TOP_UNIVPLL			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CLK_TOP_UNIVPLL_D7		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CLK_TOP_UNIVPLL_D26		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CLK_TOP_UNIVPLL_D52		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_TOP_UNIVPLL_D104		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CLK_TOP_UNIVPLL_D208		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CLK_TOP_UNIVPLL_D2		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CLK_TOP_UNIVPLL1_D2		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLK_TOP_UNIVPLL1_D4		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_TOP_UNIVPLL1_D8		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_TOP_UNIVPLL_D3		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_TOP_UNIVPLL2_D2		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_TOP_UNIVPLL2_D4		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_TOP_UNIVPLL2_D8		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_TOP_UNIVPLL_D5		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_TOP_UNIVPLL3_D2		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLK_TOP_UNIVPLL3_D4		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_TOP_UNIVPLL3_D8		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_TOP_F_MP0_PLL1		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_TOP_F_MP0_PLL2		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_TOP_F_BIG_PLL1		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_TOP_F_BIG_PLL2		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLK_TOP_F_BUS_PLL1		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_TOP_F_BUS_PLL2		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_TOP_APLL1			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_TOP_APLL1_D2		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_TOP_APLL1_D4		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_TOP_APLL1_D8		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_TOP_APLL1_D16		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_TOP_APLL2			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_TOP_APLL2_D2		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLK_TOP_APLL2_D4		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CLK_TOP_APLL2_D8		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_TOP_APLL2_D16		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_TOP_LVDSPLL			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLK_TOP_LVDSPLL_D2		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CLK_TOP_LVDSPLL_D4		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_TOP_LVDSPLL_D8		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_TOP_LVDSPLL2		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_TOP_LVDSPLL2_D2		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_TOP_LVDSPLL2_D4		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_TOP_LVDSPLL2_D8		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_TOP_ETHERPLL_125M		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_TOP_ETHERPLL_50M		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CLK_TOP_CVBS			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_TOP_CVBS_D2			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_TOP_SYS_26M			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_TOP_MMPLL			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_TOP_MMPLL_D2		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_TOP_VENCPLL			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_TOP_VENCPLL_D2		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_TOP_VCODECPLL		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_TOP_VCODECPLL_D2		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_TOP_TVDPLL			72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_TOP_TVDPLL_D2		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_TOP_TVDPLL_D4		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_TOP_TVDPLL_D8		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_TOP_TVDPLL_429M		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_TOP_TVDPLL_429M_D2		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_TOP_TVDPLL_429M_D4		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_TOP_MSDCPLL			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_TOP_MSDCPLL_D2		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_TOP_MSDCPLL_D4		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_TOP_MSDCPLL2		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_TOP_MSDCPLL2_D2		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_TOP_MSDCPLL2_D4		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_TOP_CLK26M_D2		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_TOP_D2A_ULCLK_6P5M		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_TOP_VPLL3_DPIX		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_TOP_VPLL_DPIX		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_TOP_LTEPLL_FS26M		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_TOP_DMPLL			90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_TOP_DSI0_LNTC		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_TOP_DSI1_LNTC		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_TOP_LVDSTX3_CLKDIG_CTS	93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_TOP_LVDSTX_CLKDIG_CTS	94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_TOP_CLKRTC_EXT		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_TOP_CLKRTC_INT		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_TOP_CSI0			97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_TOP_CVBSPLL			98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_TOP_AXI_SEL			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_TOP_MEM_SEL			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_TOP_MM_SEL			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_TOP_PWM_SEL			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_TOP_VDEC_SEL		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_TOP_VENC_SEL		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_TOP_MFG_SEL			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_TOP_CAMTG_SEL		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_TOP_UART_SEL		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_TOP_SPI_SEL			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_TOP_USB20_SEL		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_TOP_USB30_SEL		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_TOP_MSDC50_0_HCLK_SEL	111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_TOP_MSDC50_0_SEL		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_TOP_MSDC30_1_SEL		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_TOP_MSDC30_2_SEL		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_TOP_MSDC30_3_SEL		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_TOP_AUDIO_SEL		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_TOP_AUD_INTBUS_SEL		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_TOP_PMICSPI_SEL		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_TOP_DPILVDS1_SEL		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_TOP_ATB_SEL			120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_TOP_NR_SEL			121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_TOP_NFI2X_SEL		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_TOP_IRDA_SEL		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_TOP_CCI400_SEL		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_TOP_AUD_1_SEL		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_TOP_AUD_2_SEL		126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_TOP_MEM_MFG_IN_AS_SEL	127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_TOP_AXI_MFG_IN_AS_SEL	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_TOP_SCAM_SEL		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_TOP_NFIECC_SEL		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_TOP_PE2_MAC_P0_SEL		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_TOP_PE2_MAC_P1_SEL		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_TOP_DPILVDS_SEL		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_TOP_MSDC50_3_HCLK_SEL	134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_TOP_HDCP_SEL		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_TOP_HDCP_24M_SEL		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_TOP_RTC_SEL			137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_TOP_SPINOR_SEL		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_TOP_APLL_SEL		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_TOP_APLL2_SEL		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_TOP_A1SYS_HP_SEL		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_TOP_A2SYS_HP_SEL		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_TOP_ASM_L_SEL		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_TOP_ASM_M_SEL		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_TOP_ASM_H_SEL		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_TOP_I2SO1_SEL		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_TOP_I2SO2_SEL		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_TOP_I2SO3_SEL		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_TOP_TDMO0_SEL		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_TOP_TDMO1_SEL		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_TOP_I2SI1_SEL		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_TOP_I2SI2_SEL		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_TOP_I2SI3_SEL		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_TOP_ETHER_125M_SEL		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_TOP_ETHER_50M_SEL		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_TOP_JPGDEC_SEL		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_TOP_SPISLV_SEL		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_TOP_ETHER_50M_RMII_SEL	158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_TOP_CAM2TG_SEL		159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_TOP_DI_SEL			160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_TOP_TVD_SEL			161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_TOP_I2C_SEL			162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_TOP_PWM_INFRA_SEL		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_TOP_MSDC0P_AES_SEL		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_TOP_CMSYS_SEL		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_TOP_GCPU_SEL		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_TOP_AUD_APLL1_SEL		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_TOP_AUD_APLL2_SEL		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL	169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_TOP_APLL_DIV0		170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_TOP_APLL_DIV1		171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_TOP_APLL_DIV2		172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_TOP_APLL_DIV3		173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_TOP_APLL_DIV4		174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_TOP_APLL_DIV5		175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_TOP_APLL_DIV6		176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_TOP_APLL_DIV7		177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_TOP_APLL_DIV_PDN0		178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_TOP_APLL_DIV_PDN1		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_TOP_APLL_DIV_PDN2		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_TOP_APLL_DIV_PDN3		181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_TOP_APLL_DIV_PDN4		182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_TOP_APLL_DIV_PDN5		183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_TOP_APLL_DIV_PDN6		184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_TOP_APLL_DIV_PDN7		185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_TOP_APLL1_D3		186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_TOP_APLL1_REF_SEL		187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_TOP_APLL2_REF_SEL		188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_TOP_NFI2X_EN		189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_TOP_NFIECC_EN		190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_TOP_NFI1X_CK_EN		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_TOP_APLL2_D3		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_TOP_NR_CLK			193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* INFRACFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_INFRA_DBGCLK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_INFRA_GCE			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_INFRA_M4U			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_INFRA_KP			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_INFRA_AO_SPI0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_INFRA_AO_SPI1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_INFRA_AO_UART5		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_INFRA_NR_CLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* PERICFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_PERI_NFI			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_PERI_THERM			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_PERI_PWM0			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_PERI_PWM1			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLK_PERI_PWM2			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLK_PERI_PWM3			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_PERI_PWM4			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_PERI_PWM5			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_PERI_PWM6			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_PERI_PWM7			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_PERI_PWM			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_PERI_AP_DMA			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_PERI_MSDC30_0		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_PERI_MSDC30_1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_PERI_MSDC30_2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CLK_PERI_MSDC30_3		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_PERI_UART0			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_PERI_UART1			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_PERI_UART2			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_PERI_UART3			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_PERI_I2C0			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_PERI_I2C1			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_PERI_I2C2			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_PERI_I2C3			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_PERI_I2C4			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLK_PERI_AUXADC			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLK_PERI_SPI0			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_PERI_SPI			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK_PERI_I2C5			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_PERI_SPI2			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_PERI_SPI3			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_PERI_SPI5			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_PERI_UART4			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLK_PERI_SFLASH			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_PERI_GMAC			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLK_PERI_PCIE0			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_PERI_PCIE1			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_PERI_GMAC_PCLK		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_PERI_MSDC50_0_EN		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_PERI_MSDC30_1_EN		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_PERI_MSDC30_2_EN		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CLK_PERI_MSDC30_3_EN		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_PERI_MSDC50_0_HCLK_EN	42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CLK_PERI_MSDC50_3_HCLK_EN	43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CLK_PERI_MSDC30_0_QTR_EN	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CLK_PERI_MSDC30_3_QTR_EN	45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CLK_PERI_NR_CLK			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* MCUCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CLK_MCU_MP0_SEL			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CLK_MCU_MP2_SEL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CLK_MCU_BUS_SEL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CLK_MCU_NR_CLK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* MFGCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CLK_MFG_BG3D			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CLK_MFG_NR_CLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* MMSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CLK_MM_SMI_COMMON		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CLK_MM_SMI_LARB0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CLK_MM_CAM_MDP			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CLK_MM_MDP_RDMA0		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CLK_MM_MDP_RDMA1		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CLK_MM_MDP_RSZ0			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CLK_MM_MDP_RSZ1			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLK_MM_MDP_RSZ2			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CLK_MM_MDP_TDSHP0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CLK_MM_MDP_TDSHP1		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CLK_MM_MDP_CROP			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CLK_MM_MDP_WDMA			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CLK_MM_MDP_WROT0		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CLK_MM_MDP_WROT1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CLK_MM_FAKE_ENG			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CLK_MM_MUTEX_32K		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CLK_MM_DISP_OVL0		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CLK_MM_DISP_OVL1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CLK_MM_DISP_RDMA0		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CLK_MM_DISP_RDMA1		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CLK_MM_DISP_RDMA2		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CLK_MM_DISP_WDMA0		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CLK_MM_DISP_WDMA1		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLK_MM_DISP_COLOR0		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CLK_MM_DISP_COLOR1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CLK_MM_DISP_AAL			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CLK_MM_DISP_GAMMA		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CLK_MM_DISP_UFOE		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CLK_MM_DISP_SPLIT0		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CLK_MM_DISP_OD			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CLK_MM_DISP_PWM0_MM		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CLK_MM_DISP_PWM0_26M		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CLK_MM_DISP_PWM1_MM		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CLK_MM_DISP_PWM1_26M		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CLK_MM_DSI0_ENGINE		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CLK_MM_DSI0_DIGITAL		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CLK_MM_DSI1_ENGINE		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CLK_MM_DSI1_DIGITAL		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CLK_MM_DPI_PIXEL		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CLK_MM_DPI_ENGINE		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CLK_MM_DPI1_PIXEL		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CLK_MM_DPI1_ENGINE		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CLK_MM_LVDS_PIXEL		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CLK_MM_LVDS_CTS			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CLK_MM_SMI_LARB4		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CLK_MM_SMI_COMMON1		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define CLK_MM_SMI_LARB5		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CLK_MM_MDP_RDMA2		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CLK_MM_MDP_TDSHP2		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define CLK_MM_DISP_OVL2		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define CLK_MM_DISP_WDMA2		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CLK_MM_DISP_COLOR2		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CLK_MM_DISP_AAL1		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CLK_MM_DISP_OD1			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CLK_MM_LVDS1_PIXEL		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CLK_MM_LVDS1_CTS		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CLK_MM_SMI_LARB7		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CLK_MM_MDP_RDMA3		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CLK_MM_MDP_WROT2		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CLK_MM_DSI2			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CLK_MM_DSI2_DIGITAL		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define CLK_MM_DSI3			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CLK_MM_DSI3_DIGITAL		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CLK_MM_NR_CLK			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* IMGSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CLK_IMG_SMI_LARB2		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CLK_IMG_SENINF_SCAM_EN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CLK_IMG_SENINF_CAM_EN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define CLK_IMG_CAM_SV_EN		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CLK_IMG_CAM_SV1_EN		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CLK_IMG_CAM_SV2_EN		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CLK_IMG_NR_CLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* BDPSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CLK_BDP_BRIDGE_B		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CLK_BDP_BRIDGE_DRAM		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CLK_BDP_LARB_DRAM		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CLK_BDP_WR_CHANNEL_VDI_PXL	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CLK_BDP_WR_CHANNEL_VDI_DRAM	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CLK_BDP_WR_CHANNEL_VDI_B	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CLK_BDP_MT_B			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CLK_BDP_DISPFMT_27M		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CLK_BDP_DISPFMT_27M_VDOUT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define CLK_BDP_DISPFMT_27_74_74	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CLK_BDP_DISPFMT_2FS		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CLK_BDP_DISPFMT_2FS_2FS74_148	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CLK_BDP_DISPFMT_B		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CLK_BDP_VDO_DRAM		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CLK_BDP_VDO_2FS			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define CLK_BDP_VDO_B			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CLK_BDP_WR_CHANNEL_DI_PXL	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CLK_BDP_WR_CHANNEL_DI_DRAM	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CLK_BDP_WR_CHANNEL_DI_B		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CLK_BDP_NR_AGENT		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CLK_BDP_NR_DRAM			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CLK_BDP_NR_B			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CLK_BDP_BRIDGE_RT_B		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define CLK_BDP_BRIDGE_RT_DRAM		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define CLK_BDP_LARB_RT_DRAM		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CLK_BDP_TVD_TDC			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CLK_BDP_TVD_54			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define CLK_BDP_TVD_CBUS		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define CLK_BDP_NR_CLK			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* VDECSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CLK_VDEC_CKEN			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CLK_VDEC_LARB1_CKEN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CLK_VDEC_IMGRZ_CKEN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CLK_VDEC_NR_CLK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* VENCSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define CLK_VENC_SMI_COMMON_CON		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define CLK_VENC_VENC			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define CLK_VENC_SMI_LARB6		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define CLK_VENC_NR_CLK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* JPGDECSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CLK_JPGDEC_JPGDEC1		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CLK_JPGDEC_JPGDEC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CLK_JPGDEC_NR_CLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #endif /* _DT_BINDINGS_CLK_MT2712_H */