Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Shunli Wang <shunli.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_MT2701_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_MT2701_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* TOPCKGEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define CLK_TOP_SYSPLL				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CLK_TOP_SYSPLL_D2			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CLK_TOP_SYSPLL_D3			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CLK_TOP_SYSPLL_D5			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CLK_TOP_SYSPLL_D7			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CLK_TOP_SYSPLL1_D2			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CLK_TOP_SYSPLL1_D4			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CLK_TOP_SYSPLL1_D8			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLK_TOP_SYSPLL1_D16			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CLK_TOP_SYSPLL2_D2			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CLK_TOP_SYSPLL2_D4			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CLK_TOP_SYSPLL2_D8			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLK_TOP_SYSPLL3_D2			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLK_TOP_SYSPLL3_D4			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_TOP_SYSPLL4_D2			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_TOP_SYSPLL4_D4			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_TOP_UNIVPLL				17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLK_TOP_UNIVPLL_D2			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_TOP_UNIVPLL_D3			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLK_TOP_UNIVPLL_D5			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_TOP_UNIVPLL_D7			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLK_TOP_UNIVPLL_D26			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CLK_TOP_UNIVPLL_D52			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CLK_TOP_UNIVPLL_D108			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CLK_TOP_USB_PHY48M			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_TOP_UNIVPLL1_D2			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_TOP_UNIVPLL1_D4			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_TOP_UNIVPLL1_D8			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_TOP_UNIVPLL2_D2			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_TOP_UNIVPLL2_D4			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_TOP_UNIVPLL2_D8			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_TOP_UNIVPLL2_D16			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_TOP_UNIVPLL2_D32			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_TOP_UNIVPLL3_D2			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_TOP_UNIVPLL3_D4			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_TOP_UNIVPLL3_D8			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_TOP_MSDCPLL				37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_TOP_MSDCPLL_D2			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_TOP_MSDCPLL_D4			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_TOP_MSDCPLL_D8			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CLK_TOP_MMPLL				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CLK_TOP_MMPLL_D2			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CLK_TOP_DMPLL				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_TOP_DMPLL_D2			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CLK_TOP_DMPLL_D4			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CLK_TOP_DMPLL_X2			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CLK_TOP_TVDPLL				47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLK_TOP_TVDPLL_D2			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_TOP_TVDPLL_D4			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_TOP_TVD2PLL				50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_TOP_TVD2PLL_D2			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_TOP_HADDS2PLL_98M			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_TOP_HADDS2PLL_294M			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_TOP_HADDS2_FB			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_TOP_MIPIPLL_D2			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLK_TOP_MIPIPLL_D4			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_TOP_HDMIPLL				57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_TOP_HDMIPLL_D2			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_TOP_HDMIPLL_D3			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_TOP_HDMI_SCL_RX			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_TOP_HDMI_0_PIX340M			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLK_TOP_HDMI_0_DEEP340M			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_TOP_HDMI_0_PLL340M			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_TOP_AUD1PLL_98M			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_TOP_AUD2PLL_90M			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_TOP_AUDPLL				66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_TOP_AUDPLL_D4			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_TOP_AUDPLL_D8			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_TOP_AUDPLL_D16			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_TOP_AUDPLL_D24			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLK_TOP_ETHPLL_500M			71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CLK_TOP_VDECPLL				72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_TOP_VENCPLL				73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_TOP_MIPIPLL				74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLK_TOP_ARMPLL_1P3G			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_TOP_MM_SEL				76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_TOP_DDRPHYCFG_SEL			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_TOP_MEM_SEL				78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_TOP_AXI_SEL				79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_TOP_CAMTG_SEL			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_TOP_MFG_SEL				81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_TOP_VDEC_SEL			82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CLK_TOP_PWM_SEL				83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_TOP_MSDC30_0_SEL			84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_TOP_USB20_SEL			85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_TOP_SPI0_SEL			86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_TOP_UART_SEL			87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_TOP_AUDINTBUS_SEL			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_TOP_AUDIO_SEL			89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_TOP_MSDC30_2_SEL			90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_TOP_MSDC30_1_SEL			91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_TOP_DPI1_SEL			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_TOP_DPI0_SEL			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_TOP_SCP_SEL				94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_TOP_PMICSPI_SEL			95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_TOP_APLL_SEL			96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_TOP_HDMI_SEL			97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_TOP_TVE_SEL				98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_TOP_EMMC_HCLK_SEL			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_TOP_NFI2X_SEL			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_TOP_RTC_SEL				101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_TOP_OSD_SEL				102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_TOP_NR_SEL				103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_TOP_DI_SEL				104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_TOP_FLASH_SEL			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_TOP_ASM_M_SEL			106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_TOP_ASM_I_SEL			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_TOP_INTDIR_SEL			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_TOP_HDMIRX_BIST_SEL			109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_TOP_ETHIF_SEL			110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_TOP_MS_CARD_SEL			111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_TOP_ASM_H_SEL			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_TOP_SPI1_SEL			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_TOP_CMSYS_SEL			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_TOP_MSDC30_3_SEL			115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_TOP_HDMIRX26_24_SEL			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_TOP_AUD2DVD_SEL			117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_TOP_8BDAC_SEL			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_TOP_SPI2_SEL			119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_TOP_AUD_MUX1_SEL			120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_TOP_AUD_MUX2_SEL			121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_TOP_AUDPLL_MUX_SEL			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_TOP_AUD_K1_SRC_SEL			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_TOP_AUD_K2_SRC_SEL			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_TOP_AUD_K3_SRC_SEL			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_TOP_AUD_K4_SRC_SEL			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_TOP_AUD_K5_SRC_SEL			127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_TOP_AUD_K6_SRC_SEL			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_TOP_PADMCLK_SEL			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_TOP_AUD_EXTCK1_DIV			130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_TOP_AUD_EXTCK2_DIV			131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_TOP_AUD_MUX1_DIV			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_TOP_AUD_MUX2_DIV			133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_TOP_AUD_K1_SRC_DIV			134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_TOP_AUD_K2_SRC_DIV			135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_TOP_AUD_K3_SRC_DIV			136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_TOP_AUD_K4_SRC_DIV			137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_TOP_AUD_K5_SRC_DIV			138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_TOP_AUD_K6_SRC_DIV			139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_TOP_AUD_I2S1_MCLK			140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_TOP_AUD_I2S2_MCLK			141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_TOP_AUD_I2S3_MCLK			142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_TOP_AUD_I2S4_MCLK			143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_TOP_AUD_I2S5_MCLK			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_TOP_AUD_I2S6_MCLK			145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_TOP_AUD_48K_TIMING			146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_TOP_AUD_44K_TIMING			147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_TOP_32K_INTERNAL			148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_TOP_32K_EXTERNAL			149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_TOP_CLK26M_D8			150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_TOP_8BDAC				151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_TOP_WBG_DIG_416M			152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_TOP_DPI				153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_TOP_DSI0_LNTC_DSI			154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_TOP_AUD_EXT1			155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_TOP_AUD_EXT2			156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_TOP_NFI1X_PAD			157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_TOP_AXISEL_D4			158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_TOP_NR				159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* APMIXEDSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_APMIXED_ARMPLL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_APMIXED_MAINPLL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_APMIXED_UNIVPLL			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_APMIXED_MMPLL			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_APMIXED_MSDCPLL			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_APMIXED_TVDPLL			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_APMIXED_AUD1PLL			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_APMIXED_TRGPLL			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_APMIXED_ETHPLL			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_APMIXED_VDECPLL			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_APMIXED_HADDS2PLL			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_APMIXED_AUD2PLL			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_APMIXED_TVD2PLL			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_APMIXED_HDMI_REF			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_APMIXED_NR				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* DDRPHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_DDRPHY_VENCPLL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_DDRPHY_NR				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* INFRACFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_INFRA_DBG				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_INFRA_SMI				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_INFRA_QAXI_CM4			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_INFRA_AUD_SPLIN_B			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_INFRA_AUDIO				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_INFRA_EFUSE				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_INFRA_L2C_SRAM			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_INFRA_M4U				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_INFRA_CONNMCU			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_INFRA_TRNG				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_INFRA_RAMBUFIF			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_INFRA_CPUM				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_INFRA_KP				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_INFRA_CEC				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_INFRA_IRRX				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_INFRA_PMICSPI			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_INFRA_PMICWRAP			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_INFRA_DDCCI				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_INFRA_CLK_13M			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_INFRA_CPUSEL                        20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_INFRA_NR				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* PERICFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_PERI_NFI				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_PERI_THERM				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_PERI_PWM1				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_PERI_PWM2				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_PERI_PWM3				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_PERI_PWM4				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_PERI_PWM5				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_PERI_PWM6				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_PERI_PWM7				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_PERI_PWM				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_PERI_USB0				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_PERI_USB1				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_PERI_AP_DMA				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_PERI_MSDC30_0			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_PERI_MSDC30_1			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_PERI_MSDC30_2			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_PERI_MSDC30_3			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_PERI_MSDC50_3			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_PERI_NLI				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_PERI_UART0				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_PERI_UART1				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLK_PERI_UART2				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLK_PERI_UART3				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_PERI_BTIF				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_PERI_I2C0				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_PERI_I2C1				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_PERI_I2C2				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_PERI_I2C3				28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_PERI_AUXADC				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_PERI_SPI0				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_PERI_ETH				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_PERI_USB0_MCU			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_PERI_USB1_MCU			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_PERI_USB_SLV			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_PERI_GCPU				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_PERI_NFI_ECC			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_PERI_NFI_PAD			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_PERI_FLASH				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_PERI_HOST89_INT			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_PERI_HOST89_SPI			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_PERI_HOST89_DVD			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLK_PERI_SPI1				42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLK_PERI_SPI2				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_PERI_FCI				44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_PERI_UART0_SEL			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_PERI_UART1_SEL			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_PERI_UART2_SEL			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_PERI_UART3_SEL			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLK_PERI_NR				49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* AUDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_AUD_AFE				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_AUD_LRCK_DETECT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_AUD_I2S				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_AUD_APLL_TUNER			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CLK_AUD_HDMI				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_AUD_SPDF				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CLK_AUD_SPDF2				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CLK_AUD_APLL				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CLK_AUD_TML				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CLK_AUD_AHB_IDLE_EXT			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CLK_AUD_AHB_IDLE_INT			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CLK_AUD_I2SIN1				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CLK_AUD_I2SIN2				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CLK_AUD_I2SIN3				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CLK_AUD_I2SIN4				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CLK_AUD_I2SIN5				16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CLK_AUD_I2SIN6				17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CLK_AUD_I2SO1				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CLK_AUD_I2SO2				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CLK_AUD_I2SO3				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CLK_AUD_I2SO4				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CLK_AUD_I2SO5				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CLK_AUD_I2SO6				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CLK_AUD_ASRCI1				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CLK_AUD_ASRCI2				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CLK_AUD_ASRCO1				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CLK_AUD_ASRCO2				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CLK_AUD_ASRC11				28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CLK_AUD_ASRC12				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CLK_AUD_HDMIRX				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CLK_AUD_INTDIR				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLK_AUD_A1SYS				32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CLK_AUD_A2SYS				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CLK_AUD_AFE_CONN			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CLK_AUD_AFE_PCMIF			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CLK_AUD_AFE_MRGIF			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CLK_AUD_MMIF_UL1			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CLK_AUD_MMIF_UL2			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CLK_AUD_MMIF_UL3			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CLK_AUD_MMIF_UL4			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CLK_AUD_MMIF_UL5			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CLK_AUD_MMIF_UL6			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CLK_AUD_MMIF_DL1			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CLK_AUD_MMIF_DL2			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CLK_AUD_MMIF_DL3			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CLK_AUD_MMIF_DL4			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLK_AUD_MMIF_DL5			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CLK_AUD_MMIF_DL6			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CLK_AUD_MMIF_DLMCH			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CLK_AUD_MMIF_ARB1			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CLK_AUD_MMIF_AWB1			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CLK_AUD_MMIF_AWB2			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CLK_AUD_MMIF_DAI			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CLK_AUD_DMIC1				54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CLK_AUD_DMIC2				55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CLK_AUD_ASRCI3				56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CLK_AUD_ASRCI4				57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CLK_AUD_ASRCI5				58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CLK_AUD_ASRCI6				59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CLK_AUD_ASRCO3				60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CLK_AUD_ASRCO4				61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CLK_AUD_ASRCO5				62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CLK_AUD_ASRCO6				63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CLK_AUD_MEM_ASRC1			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CLK_AUD_MEM_ASRC2			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CLK_AUD_MEM_ASRC3			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CLK_AUD_MEM_ASRC4			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CLK_AUD_MEM_ASRC5			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define CLK_AUD_DSD_ENC				69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CLK_AUD_ASRC_BRG			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CLK_AUD_NR				71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* MMSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CLK_MM_SMI_COMMON			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CLK_MM_SMI_LARB0			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CLK_MM_CMDQ				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CLK_MM_MUTEX				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CLK_MM_DISP_COLOR			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CLK_MM_DISP_BLS				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CLK_MM_DISP_WDMA			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CLK_MM_DISP_RDMA			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CLK_MM_DISP_OVL				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define CLK_MM_MDP_TDSHP			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CLK_MM_MDP_WROT				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CLK_MM_MDP_WDMA				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define CLK_MM_MDP_RSZ1				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CLK_MM_MDP_RSZ0				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CLK_MM_MDP_RDMA				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CLK_MM_MDP_BLS_26M			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CLK_MM_CAM_MDP				17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CLK_MM_FAKE_ENG				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define CLK_MM_MUTEX_32K			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CLK_MM_DISP_RDMA1			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CLK_MM_DISP_UFOE			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CLK_MM_DSI_ENGINE			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CLK_MM_DSI_DIG				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CLK_MM_DPI_DIGL				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CLK_MM_DPI_ENGINE			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CLK_MM_DPI1_DIGL			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CLK_MM_DPI1_ENGINE			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CLK_MM_TVE_OUTPUT			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CLK_MM_TVE_INPUT			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CLK_MM_HDMI_PIXEL			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CLK_MM_HDMI_PLL				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CLK_MM_HDMI_AUDIO			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CLK_MM_HDMI_SPDIF			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define CLK_MM_TVE_FMM				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CLK_MM_NR				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* IMGSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CLK_IMG_SMI_COMM			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define CLK_IMG_RESZ				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CLK_IMG_JPGDEC_SMI			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CLK_IMG_JPGDEC				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CLK_IMG_VENC_LT				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CLK_IMG_VENC				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CLK_IMG_NR				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* VDEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define CLK_VDEC_CKGEN				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CLK_VDEC_LARB				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CLK_VDEC_NR				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* HIFSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CLK_HIFSYS_USB0PHY			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CLK_HIFSYS_USB1PHY			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CLK_HIFSYS_PCIE0			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CLK_HIFSYS_PCIE1			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CLK_HIFSYS_PCIE2			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CLK_HIFSYS_NR				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* ETHSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CLK_ETHSYS_HSDMA			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define CLK_ETHSYS_ESW				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define CLK_ETHSYS_GP2				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define CLK_ETHSYS_GP1				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define CLK_ETHSYS_PCM				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CLK_ETHSYS_GDMA				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CLK_ETHSYS_I2S				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define CLK_ETHSYS_CRYPTO			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CLK_ETHSYS_NR				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* G3DSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define CLK_G3DSYS_CORE				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CLK_G3DSYS_NR				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* BDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CLK_BDP_BRG_BA				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CLK_BDP_BRG_DRAM			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CLK_BDP_LARB_DRAM			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define CLK_BDP_WR_VDI_PXL			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CLK_BDP_WR_VDI_DRAM			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define CLK_BDP_WR_B				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define CLK_BDP_DGI_IN				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CLK_BDP_DGI_OUT				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define CLK_BDP_FMT_MAST_27			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define CLK_BDP_FMT_B				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CLK_BDP_OSD_B				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define CLK_BDP_OSD_DRAM			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define CLK_BDP_OSD_AGENT			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define CLK_BDP_OSD_PXL				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define CLK_BDP_RLE_B				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define CLK_BDP_RLE_AGENT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define CLK_BDP_RLE_DRAM			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define CLK_BDP_F27M				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define CLK_BDP_F27M_VDOUT			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define CLK_BDP_F27_74_74			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define CLK_BDP_F2FS				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define CLK_BDP_F2FS74_148			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define CLK_BDP_FB				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define CLK_BDP_VDO_DRAM			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define CLK_BDP_VDO_2FS				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define CLK_BDP_VDO_B				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define CLK_BDP_WR_DI_PXL			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define CLK_BDP_WR_DI_DRAM			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define CLK_BDP_WR_DI_B				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define CLK_BDP_NR_PXL				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define CLK_BDP_NR_DRAM				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define CLK_BDP_NR_B				32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define CLK_BDP_RX_F				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define CLK_BDP_RX_X				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define CLK_BDP_RXPDT				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define CLK_BDP_RX_CSCL_N			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define CLK_BDP_RX_CSCL				37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define CLK_BDP_RX_DDCSCL_N			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define CLK_BDP_RX_DDCSCL			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define CLK_BDP_RX_VCO				40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define CLK_BDP_RX_DP				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define CLK_BDP_RX_P				42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define CLK_BDP_RX_M				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define CLK_BDP_RX_PLL				44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define CLK_BDP_BRG_RT_B			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define CLK_BDP_BRG_RT_DRAM			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define CLK_BDP_LARBRT_DRAM			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define CLK_BDP_TMDS_SYN			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define CLK_BDP_HDMI_MON			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define CLK_BDP_NR				50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #endif /* _DT_BINDINGS_CLK_MT2701_H */