Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides constants for MPC512x clock specs in DT bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define MPC512x_CLK_DUMMY		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MPC512x_CLK_REF			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MPC512x_CLK_SYS			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MPC512x_CLK_DIU			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MPC512x_CLK_VIU			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MPC512x_CLK_CSB			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MPC512x_CLK_E300		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MPC512x_CLK_IPS			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MPC512x_CLK_FEC			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MPC512x_CLK_SATA		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MPC512x_CLK_PATA		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MPC512x_CLK_NFC			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MPC512x_CLK_LPC			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MPC512x_CLK_MBX_BUS		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPC512x_CLK_MBX			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPC512x_CLK_MBX_3D		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPC512x_CLK_AXE			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPC512x_CLK_USB1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPC512x_CLK_USB2		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MPC512x_CLK_I2C			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MPC512x_CLK_MSCAN0_MCLK		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MPC512x_CLK_MSCAN1_MCLK		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MPC512x_CLK_MSCAN2_MCLK		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MPC512x_CLK_MSCAN3_MCLK		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MPC512x_CLK_BDLC		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MPC512x_CLK_SDHC		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MPC512x_CLK_PCI			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MPC512x_CLK_PSC_MCLK_IN		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MPC512x_CLK_SPDIF_TX		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPC512x_CLK_SPDIF_RX		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MPC512x_CLK_SPDIF_MCLK		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MPC512x_CLK_SPDIF		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MPC512x_CLK_AC97		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MPC512x_CLK_PSC0_MCLK		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MPC512x_CLK_PSC1_MCLK		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPC512x_CLK_PSC2_MCLK		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPC512x_CLK_PSC3_MCLK		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MPC512x_CLK_PSC4_MCLK		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MPC512x_CLK_PSC5_MCLK		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MPC512x_CLK_PSC6_MCLK		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MPC512x_CLK_PSC7_MCLK		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MPC512x_CLK_PSC8_MCLK		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MPC512x_CLK_PSC9_MCLK		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MPC512x_CLK_PSC10_MCLK		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPC512x_CLK_PSC11_MCLK		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MPC512x_CLK_PSC_FIFO		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MPC512x_CLK_PSC0		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MPC512x_CLK_PSC1		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MPC512x_CLK_PSC2		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MPC512x_CLK_PSC3		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MPC512x_CLK_PSC4		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MPC512x_CLK_PSC5		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MPC512x_CLK_PSC6		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MPC512x_CLK_PSC7		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MPC512x_CLK_PSC8		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MPC512x_CLK_PSC9		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MPC512x_CLK_PSC10		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MPC512x_CLK_PSC11		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MPC512x_CLK_SDHC2		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MPC512x_CLK_FEC2		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MPC512x_CLK_OUT0_CLK		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MPC512x_CLK_OUT1_CLK		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MPC512x_CLK_OUT2_CLK		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MPC512x_CLK_OUT3_CLK		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MPC512x_CLK_CAN_CLK_IN		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MPC512x_CLK_LAST_PUBLIC		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif