Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2019 Microchip Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Lars Povlsen <lars.povlsen@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _DT_BINDINGS_CLK_SPARX5_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _DT_BINDINGS_CLK_SPARX5_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLK_ID_CORE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_ID_DDR	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_ID_CPU2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_ID_ARM2	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_ID_AUX1	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_ID_AUX2	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_ID_AUX3	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_ID_AUX4	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_ID_SYNCE	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define N_CLOCKS	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif