Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Purna Chandra Mandal,<purna.mandal@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* clock output indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define POSCCLK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define FRCCLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BFRCCLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LPRCCLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SOSCCLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FRCDIVCLK	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLLCLK		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SCLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PB1CLK		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PB2CLK		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PB3CLK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PB4CLK		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PB5CLK		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PB6CLK		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PB7CLK		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REF1CLK		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REF2CLK		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REF3CLK		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REF4CLK		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REF5CLK		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UPLLCLK		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MAXCLKS		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif	/* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */