^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Google, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Device Tree binding constants clocks for the Maxim 77802 PMIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Fixed rate clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MAX77802_CLK_32K_AP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MAX77802_CLK_32K_CP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Total number of clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */