Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __DTS_MARVELL_PXA1928_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __DTS_MARVELL_PXA1928_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Clock ID values here correspond to the control register offset/4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* apb peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PXA1928_CLK_RTC			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PXA1928_CLK_TWSI0		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PXA1928_CLK_TWSI1		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PXA1928_CLK_TWSI2		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PXA1928_CLK_TWSI3		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PXA1928_CLK_OWIRE		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PXA1928_CLK_KPC			0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PXA1928_CLK_TB_ROTARY		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PXA1928_CLK_SW_JTAG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PXA1928_CLK_TIMER1		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PXA1928_CLK_UART0		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PXA1928_CLK_UART1		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PXA1928_CLK_UART2		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PXA1928_CLK_GPIO		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PXA1928_CLK_PWM0		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PXA1928_CLK_PWM1		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PXA1928_CLK_PWM2		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PXA1928_CLK_PWM3		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PXA1928_CLK_SSP0		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PXA1928_CLK_SSP1		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PXA1928_CLK_SSP2		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PXA1928_CLK_TWSI4		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PXA1928_CLK_TWSI5		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PXA1928_CLK_UART3		0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PXA1928_CLK_THSENS_GLOB		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PXA1928_CLK_THSENS_CPU		0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PXA1928_CLK_THSENS_VPU		0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PXA1928_CLK_THSENS_GC		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PXA1928_APBC_NR_CLKS		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* axi peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PXA1928_CLK_SDH0		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PXA1928_CLK_SDH1		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PXA1928_CLK_USB			0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PXA1928_CLK_NAND		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PXA1928_CLK_DMA			0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PXA1928_CLK_SDH2		0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PXA1928_CLK_SDH3		0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PXA1928_CLK_HSIC		0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PXA1928_CLK_SDH4		0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PXA1928_CLK_GC3D		0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PXA1928_CLK_GC2D		0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PXA1928_APMU_NR_CLKS		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif