Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __DTS_MARVELL_PXA168_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __DTS_MARVELL_PXA168_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* fixed clocks and plls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define PXA168_CLK_CLK32		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define PXA168_CLK_VCTCXO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define PXA168_CLK_PLL1			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define PXA168_CLK_PLL1_2		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PXA168_CLK_PLL1_4		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PXA168_CLK_PLL1_8		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PXA168_CLK_PLL1_16		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PXA168_CLK_PLL1_6		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PXA168_CLK_PLL1_12		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PXA168_CLK_PLL1_24		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PXA168_CLK_PLL1_48		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PXA168_CLK_PLL1_96		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PXA168_CLK_PLL1_13		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PXA168_CLK_PLL1_13_1_5		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PXA168_CLK_PLL1_2_1_5		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PXA168_CLK_PLL1_3_16		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PXA168_CLK_PLL1_192		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PXA168_CLK_UART_PLL		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PXA168_CLK_USB_PLL		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* apb periphrals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PXA168_CLK_TWSI0		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PXA168_CLK_TWSI1		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PXA168_CLK_TWSI2		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PXA168_CLK_TWSI3		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PXA168_CLK_GPIO			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PXA168_CLK_KPC			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PXA168_CLK_RTC			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PXA168_CLK_PWM0			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PXA168_CLK_PWM1			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PXA168_CLK_PWM2			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PXA168_CLK_PWM3			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PXA168_CLK_UART0		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PXA168_CLK_UART1		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PXA168_CLK_UART2		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PXA168_CLK_SSP0			74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PXA168_CLK_SSP1			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PXA168_CLK_SSP2			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PXA168_CLK_SSP3			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PXA168_CLK_SSP4			78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PXA168_CLK_TIMER		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* axi periphrals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PXA168_CLK_DFC			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PXA168_CLK_SDH0			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PXA168_CLK_SDH1			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PXA168_CLK_SDH2			103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PXA168_CLK_USB			104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PXA168_CLK_SPH			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PXA168_CLK_DISP0		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PXA168_CLK_CCIC0		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PXA168_CLK_CCIC0_PHY		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PXA168_CLK_CCIC0_SPHY		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PXA168_NR_CLKS			200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif