^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __DTS_MARVELL_MMP2_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __DTS_MARVELL_MMP2_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* fixed clocks and plls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define MMP2_CLK_CLK32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define MMP2_CLK_VCTCXO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define MMP2_CLK_PLL1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MMP2_CLK_PLL1_2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MMP2_CLK_PLL1_4 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MMP2_CLK_PLL1_8 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MMP2_CLK_PLL1_16 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MMP2_CLK_PLL1_3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MMP2_CLK_PLL1_6 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MMP2_CLK_PLL1_12 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MMP2_CLK_PLL1_20 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MMP2_CLK_PLL2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MMP2_CLK_PLL2_2 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MMP2_CLK_PLL2_4 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MMP2_CLK_PLL2_8 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MMP2_CLK_PLL2_16 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MMP2_CLK_PLL2_3 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MMP2_CLK_PLL2_6 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MMP2_CLK_PLL2_12 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MMP2_CLK_VCTCXO_2 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MMP2_CLK_VCTCXO_4 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MMP2_CLK_UART_PLL 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MMP2_CLK_USB_PLL 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MMP3_CLK_PLL1_P 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MMP3_CLK_PLL2_P 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MMP3_CLK_PLL3 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MMP2_CLK_I2S0 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MMP2_CLK_I2S1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* apb periphrals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MMP2_CLK_TWSI0 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MMP2_CLK_TWSI1 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MMP2_CLK_TWSI2 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MMP2_CLK_TWSI3 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MMP2_CLK_TWSI4 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MMP2_CLK_TWSI5 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MMP2_CLK_GPIO 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MMP2_CLK_KPC 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MMP2_CLK_RTC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MMP2_CLK_PWM0 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MMP2_CLK_PWM1 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MMP2_CLK_PWM2 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMP2_CLK_PWM3 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MMP2_CLK_UART0 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MMP2_CLK_UART1 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MMP2_CLK_UART2 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MMP2_CLK_UART3 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MMP2_CLK_SSP0 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MMP2_CLK_SSP1 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MMP2_CLK_SSP2 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MMP2_CLK_SSP3 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MMP2_CLK_TIMER 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MMP2_CLK_THERMAL0 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MMP3_CLK_THERMAL1 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MMP3_CLK_THERMAL2 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MMP3_CLK_THERMAL3 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* axi periphrals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MMP2_CLK_SDH0 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MMP2_CLK_SDH1 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MMP2_CLK_SDH2 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MMP2_CLK_SDH3 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MMP2_CLK_USB 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MMP2_CLK_DISP0 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MMP2_CLK_DISP0_MUX 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MMP2_CLK_DISP0_SPHY 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MMP2_CLK_DISP1 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MMP2_CLK_DISP1_MUX 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MMP2_CLK_CCIC_ARBITER 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MMP2_CLK_CCIC0 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MMP2_CLK_CCIC0_MIX 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MMP2_CLK_CCIC0_PHY 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MMP2_CLK_CCIC0_SPHY 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MMP2_CLK_CCIC1 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MMP2_CLK_CCIC1_MIX 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MMP2_CLK_CCIC1_PHY 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MMP2_CLK_CCIC1_SPHY 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MMP2_CLK_DISP0_LCDC 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MMP2_CLK_USBHSIC0 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MMP2_CLK_USBHSIC1 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MMP2_CLK_GPU_BUS 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MMP2_CLK_GPU_3D 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MMP3_CLK_GPU_2D 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MMP3_CLK_SDH4 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MMP2_CLK_AUDIO 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MMP2_NR_CLKS 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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