Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This code is released using a dual license strategy: BSD/GPL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * You can choose the licence that better fits your requirements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Released under the terms of 3-clause BSD License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Released under the terms of GNU General Public License Version 2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __DT_BINDINGS_LPC32XX_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __DT_BINDINGS_LPC32XX_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* LPC32XX System Control Block clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LPC32XX_CLK_RTC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LPC32XX_CLK_DMA		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LPC32XX_CLK_MLC		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LPC32XX_CLK_SLC		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPC32XX_CLK_LCD		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPC32XX_CLK_MAC		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPC32XX_CLK_SD		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPC32XX_CLK_DDRAM	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LPC32XX_CLK_SSP0	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPC32XX_CLK_SSP1	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPC32XX_CLK_UART3	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LPC32XX_CLK_UART4	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LPC32XX_CLK_UART5	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPC32XX_CLK_UART6	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPC32XX_CLK_IRDA	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPC32XX_CLK_I2C1	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPC32XX_CLK_I2C2	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPC32XX_CLK_TIMER0	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPC32XX_CLK_TIMER1	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPC32XX_CLK_TIMER2	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPC32XX_CLK_TIMER3	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPC32XX_CLK_TIMER4	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPC32XX_CLK_TIMER5	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPC32XX_CLK_WDOG	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPC32XX_CLK_I2S0	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPC32XX_CLK_I2S1	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPC32XX_CLK_SPI1	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPC32XX_CLK_SPI2	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPC32XX_CLK_MCPWM	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LPC32XX_CLK_HSTIMER	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPC32XX_CLK_KEY		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LPC32XX_CLK_PWM1	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LPC32XX_CLK_PWM2	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LPC32XX_CLK_ADC		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LPC32XX_CLK_HCLK_PLL	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LPC32XX_CLK_PERIPH	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* LPC32XX USB clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LPC32XX_USB_CLK_I2C	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LPC32XX_USB_CLK_DEVICE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LPC32XX_USB_CLK_HOST	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */