Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This code is released using a dual license strategy: BSD/GPL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * You can choose the licence that better fits your requirements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Released under the terms of 3-clause BSD License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Released under the terms of GNU General Public License Version 2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* LPC18xx/43xx base clock ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BASE_SAFE_CLK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BASE_USB0_CLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BASE_PERIPH_CLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BASE_USB1_CLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BASE_CPU_CLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BASE_SPIFI_CLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BASE_SPI_CLK		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BASE_PHY_RX_CLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BASE_PHY_TX_CLK		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BASE_APB1_CLK		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BASE_APB3_CLK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BASE_LCD_CLK		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BASE_ADCHS_CLK		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BASE_SDIO_CLK		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BASE_SSP0_CLK		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BASE_SSP1_CLK		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BASE_UART0_CLK		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BASE_UART1_CLK		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BASE_UART2_CLK		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BASE_UART3_CLK		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BASE_OUT_CLK		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BASE_RES1_CLK		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BASE_RES2_CLK		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BASE_RES3_CLK		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BASE_RES4_CLK		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BASE_AUDIO_CLK		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BASE_CGU_OUT0_CLK	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BASE_CGU_OUT1_CLK	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BASE_CLK_MAX		(BASE_CGU_OUT1_CLK + 1)