Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (c) 2020 Western Digital Corporation or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef K210_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define K210_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * Arbitrary identifiers for clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * The structure is: in0 -> pll0 -> aclk -> cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * Since we use the hardware defaults for now, set all these to the same clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define K210_CLK_PLL0   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define K210_CLK_PLL1   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define K210_CLK_ACLK   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define K210_CLK_CPU    0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif /* K210_CLK_H */