Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides clock numbers for the ingenic,jz4770-cgu DT binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define JZ4770_CLK_EXT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define JZ4770_CLK_OSC32K	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define JZ4770_CLK_PLL0		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define JZ4770_CLK_PLL1		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define JZ4770_CLK_CCLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define JZ4770_CLK_H0CLK	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define JZ4770_CLK_H1CLK	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define JZ4770_CLK_H2CLK	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define JZ4770_CLK_C1CLK	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define JZ4770_CLK_PCLK		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define JZ4770_CLK_MMC0_MUX	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define JZ4770_CLK_MMC0		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define JZ4770_CLK_MMC1_MUX	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define JZ4770_CLK_MMC1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define JZ4770_CLK_MMC2_MUX	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define JZ4770_CLK_MMC2		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define JZ4770_CLK_CIM		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define JZ4770_CLK_UHC		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define JZ4770_CLK_GPU		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define JZ4770_CLK_BCH		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define JZ4770_CLK_LPCLK_MUX	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define JZ4770_CLK_GPS		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define JZ4770_CLK_SSI_MUX	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define JZ4770_CLK_PCM_MUX	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define JZ4770_CLK_I2S		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define JZ4770_CLK_OTG		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define JZ4770_CLK_SSI0		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define JZ4770_CLK_SSI1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define JZ4770_CLK_SSI2		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define JZ4770_CLK_PCM0		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define JZ4770_CLK_PCM1		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define JZ4770_CLK_DMA		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define JZ4770_CLK_I2C0		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define JZ4770_CLK_I2C1		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define JZ4770_CLK_I2C2		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define JZ4770_CLK_UART0	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define JZ4770_CLK_UART1	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define JZ4770_CLK_UART2	37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define JZ4770_CLK_UART3	38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define JZ4770_CLK_IPU		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define JZ4770_CLK_ADC		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define JZ4770_CLK_AIC		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define JZ4770_CLK_AUX		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define JZ4770_CLK_VPU		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define JZ4770_CLK_UHC_PHY	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define JZ4770_CLK_OTG_PHY	45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define JZ4770_CLK_EXT512	46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define JZ4770_CLK_RTC		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */