Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides clock numbers for the ingenic,jz4740-cgu DT binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * They are roughly ordered as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *   - external clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *   - PLLs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *   - muxes/dividers in the order they appear in the jz4740 programmers manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *   - gates in order of their bit in the CLKGR* registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define JZ4740_CLK_EXT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define JZ4740_CLK_RTC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define JZ4740_CLK_PLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define JZ4740_CLK_PLL_HALF	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define JZ4740_CLK_CCLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define JZ4740_CLK_HCLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define JZ4740_CLK_PCLK		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define JZ4740_CLK_MCLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define JZ4740_CLK_LCD		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define JZ4740_CLK_LCD_PCLK	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define JZ4740_CLK_I2S		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define JZ4740_CLK_SPI		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define JZ4740_CLK_MMC		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define JZ4740_CLK_UHC		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define JZ4740_CLK_UDC		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define JZ4740_CLK_UART0	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define JZ4740_CLK_UART1	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define JZ4740_CLK_DMA		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define JZ4740_CLK_IPU		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define JZ4740_CLK_ADC		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define JZ4740_CLK_I2C		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define JZ4740_CLK_AIC		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define JZ4740_CLK_TCU		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */