Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define JZ4725B_CLK_EXT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define JZ4725B_CLK_OSC32K	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define JZ4725B_CLK_PLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define JZ4725B_CLK_PLL_HALF	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define JZ4725B_CLK_CCLK	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define JZ4725B_CLK_HCLK	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define JZ4725B_CLK_PCLK	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define JZ4725B_CLK_MCLK	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define JZ4725B_CLK_IPU		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define JZ4725B_CLK_LCD		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define JZ4725B_CLK_I2S		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define JZ4725B_CLK_SPI		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define JZ4725B_CLK_MMC_MUX	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define JZ4725B_CLK_UDC		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define JZ4725B_CLK_UART	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define JZ4725B_CLK_DMA		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define JZ4725B_CLK_ADC		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define JZ4725B_CLK_I2C		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define JZ4725B_CLK_AIC		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define JZ4725B_CLK_MMC0	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define JZ4725B_CLK_MMC1	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define JZ4725B_CLK_BCH		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define JZ4725B_CLK_TCU		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define JZ4725B_CLK_EXT512	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define JZ4725B_CLK_RTC		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define JZ4725B_CLK_UDC_PHY	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */