^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Lei Chuanhua <Chuanhua.lei@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Zhu Yixin <Yixin.zhu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __INTEL_LGM_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __INTEL_LGM_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* PLL clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define LGM_CLK_OSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define LGM_CLK_PLLPP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LGM_CLK_PLL2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LGM_CLK_PLL0CZ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define LGM_CLK_PLL0B 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LGM_CLK_PLL1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LGM_CLK_LJPLL3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LGM_CLK_LJPLL4 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LGM_CLK_PLL0CM0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LGM_CLK_PLL0CM1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* clocks from PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* ROPLL clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LGM_CLK_PP_HW 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LGM_CLK_PP_UC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LGM_CLK_PP_FXD 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LGM_CLK_PP_TBM 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* PLL2 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LGM_CLK_DDR 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* PLL0CZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LGM_CLK_CM 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LGM_CLK_IC 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LGM_CLK_SDXC3 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* PLL0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LGM_CLK_NGI 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LGM_CLK_NOC4 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LGM_CLK_SW 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LGM_CLK_QSPI 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LGM_CLK_CQEM LGM_CLK_SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LGM_CLK_EMMC5 LGM_CLK_NOC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LGM_CLK_CT 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LGM_CLK_DSP 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LGM_CLK_VIF 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* LJPLL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LGM_CLK_CML 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LGM_CLK_SERDES 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LGM_CLK_POOL 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LGM_CLK_PTP 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* LJPLL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LGM_CLK_PCIE 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LGM_CLK_SATA LGM_CLK_PCIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* PLL0CM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LGM_CLK_CPU0 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* PLL0CM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LGM_CLK_CPU1 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Miscellaneous clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LGM_CLK_EMMC4 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LGM_CLK_SDXC2 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LGM_CLK_EMMC 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LGM_CLK_SDXC 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LGM_CLK_SLIC 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LGM_CLK_DCL 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LGM_CLK_DOCSIS 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LGM_CLK_PCM 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LGM_CLK_DDR_PHY 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LGM_CLK_PONDEF 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LGM_CLK_PL25M 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LGM_CLK_PL10M 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LGM_CLK_PL1544K 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LGM_CLK_PL2048K 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LGM_CLK_PL8K 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LGM_CLK_PON_NTR 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LGM_CLK_SYNC0 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LGM_CLK_SYNC1 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LGM_CLK_PROGDIV 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LGM_CLK_OD0 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LGM_CLK_OD1 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LGM_CLK_CBPHY0 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LGM_CLK_CBPHY1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LGM_CLK_CBPHY2 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LGM_CLK_CBPHY3 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Gate CLK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LGM_GCLK_C55 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LGM_GCLK_QSPI 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LGM_GCLK_EIP197 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LGM_GCLK_VAULT 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LGM_GCLK_TOE 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LGM_GCLK_SDXC 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LGM_GCLK_EMMC 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LGM_GCLK_SPI_DBG 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LGM_GCLK_DMA3 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Gate CLK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LGM_GCLK_DMA0 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LGM_GCLK_LEDC0 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LGM_GCLK_LEDC1 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LGM_GCLK_I2S0 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LGM_GCLK_I2S1 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LGM_GCLK_EBU 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LGM_GCLK_PWM 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LGM_GCLK_I2C0 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LGM_GCLK_I2C1 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LGM_GCLK_I2C2 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LGM_GCLK_I2C3 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LGM_GCLK_SSC0 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LGM_GCLK_SSC1 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LGM_GCLK_SSC2 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LGM_GCLK_SSC3 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LGM_GCLK_GPTC0 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LGM_GCLK_GPTC1 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LGM_GCLK_GPTC2 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LGM_GCLK_GPTC3 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LGM_GCLK_ASC0 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LGM_GCLK_ASC1 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LGM_GCLK_ASC2 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LGM_GCLK_ASC3 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LGM_GCLK_PCM0 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LGM_GCLK_PCM1 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LGM_GCLK_PCM2 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Gate CLK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LGM_GCLK_PCIE10 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LGM_GCLK_PCIE11 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LGM_GCLK_PCIE30 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LGM_GCLK_PCIE31 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LGM_GCLK_PCIE20 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LGM_GCLK_PCIE21 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LGM_GCLK_PCIE40 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LGM_GCLK_PCIE41 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LGM_GCLK_XPCS0 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LGM_GCLK_XPCS1 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LGM_GCLK_XPCS2 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LGM_GCLK_XPCS3 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LGM_GCLK_SATA0 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LGM_GCLK_SATA1 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LGM_GCLK_SATA2 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LGM_GCLK_SATA3 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Gate CLK3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define LGM_GCLK_ARCEM4 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LGM_GCLK_IDMAR1 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LGM_GCLK_IDMAT0 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LGM_GCLK_IDMAT1 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LGM_GCLK_IDMAT2 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LGM_GCLK_PPV4 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LGM_GCLK_GSWIPO 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LGM_GCLK_CQEM 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LGM_GCLK_XPCS5 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define LGM_GCLK_USB1 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LGM_GCLK_USB2 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif /* __INTEL_LGM_CLK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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