Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2017 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define __DT_BINDINGS_CLOCK_IMX8MQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define IMX8MQ_CLK_DUMMY		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define IMX8MQ_CLK_32K			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define IMX8MQ_CLK_25M			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define IMX8MQ_CLK_27M			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define IMX8MQ_CLK_EXT1			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define IMX8MQ_CLK_EXT2			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IMX8MQ_CLK_EXT3			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IMX8MQ_CLK_EXT4			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* ANAMIX PLL clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* FRAC PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* ARM PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IMX8MQ_ARM_PLL_REF_SEL		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IMX8MQ_ARM_PLL_REF_DIV		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IMX8MQ_ARM_PLL			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IMX8MQ_ARM_PLL_BYPASS		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IMX8MQ_ARM_PLL_OUT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* GPU PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IMX8MQ_GPU_PLL_REF_SEL		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IMX8MQ_GPU_PLL_REF_DIV		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IMX8MQ_GPU_PLL			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IMX8MQ_GPU_PLL_BYPASS		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IMX8MQ_GPU_PLL_OUT		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* VPU PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IMX8MQ_VPU_PLL_REF_SEL		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IMX8MQ_VPU_PLL_REF_DIV		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IMX8MQ_VPU_PLL			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IMX8MQ_VPU_PLL_BYPASS		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IMX8MQ_VPU_PLL_OUT		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* AUDIO PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IMX8MQ_AUDIO_PLL1_REF_SEL	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IMX8MQ_AUDIO_PLL1_REF_DIV	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IMX8MQ_AUDIO_PLL1		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IMX8MQ_AUDIO_PLL1_BYPASS	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IMX8MQ_AUDIO_PLL1_OUT		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* AUDIO PLL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IMX8MQ_AUDIO_PLL2_REF_SEL	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IMX8MQ_AUDIO_PLL2_REF_DIV	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IMX8MQ_AUDIO_PLL2		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IMX8MQ_AUDIO_PLL2_BYPASS	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IMX8MQ_AUDIO_PLL2_OUT		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* VIDEO PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IMX8MQ_VIDEO_PLL1_REF_SEL	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IMX8MQ_VIDEO_PLL1_REF_DIV	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IMX8MQ_VIDEO_PLL1		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IMX8MQ_VIDEO_PLL1_BYPASS	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IMX8MQ_VIDEO_PLL1_OUT		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* SYS1 PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IMX8MQ_SYS1_PLL1_REF_SEL	38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IMX8MQ_SYS1_PLL1_REF_DIV	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IMX8MQ_SYS1_PLL1		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IMX8MQ_SYS1_PLL1_OUT		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IMX8MQ_SYS1_PLL1_OUT_DIV	42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IMX8MQ_SYS1_PLL2		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IMX8MQ_SYS1_PLL2_DIV		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IMX8MQ_SYS1_PLL2_OUT		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* SYS2 PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IMX8MQ_SYS2_PLL1_REF_SEL	46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IMX8MQ_SYS2_PLL1_REF_DIV	47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IMX8MQ_SYS2_PLL1		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IMX8MQ_SYS2_PLL1_OUT		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define IMX8MQ_SYS2_PLL1_OUT_DIV	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IMX8MQ_SYS2_PLL2		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define IMX8MQ_SYS2_PLL2_DIV		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IMX8MQ_SYS2_PLL2_OUT		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* SYS3 PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IMX8MQ_SYS3_PLL1_REF_SEL	54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IMX8MQ_SYS3_PLL1_REF_DIV	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IMX8MQ_SYS3_PLL1		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IMX8MQ_SYS3_PLL1_OUT		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IMX8MQ_SYS3_PLL1_OUT_DIV	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IMX8MQ_SYS3_PLL2		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IMX8MQ_SYS3_PLL2_DIV		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define IMX8MQ_SYS3_PLL2_OUT		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* DRAM PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define IMX8MQ_DRAM_PLL1_REF_SEL	62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define IMX8MQ_DRAM_PLL1_REF_DIV	63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IMX8MQ_DRAM_PLL1		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IMX8MQ_DRAM_PLL1_OUT		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IMX8MQ_DRAM_PLL1_OUT_DIV	66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define IMX8MQ_DRAM_PLL2		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX8MQ_DRAM_PLL2_DIV		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX8MQ_DRAM_PLL2_OUT		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* SYS PLL DIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX8MQ_SYS1_PLL_40M		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX8MQ_SYS1_PLL_80M		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX8MQ_SYS1_PLL_100M		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX8MQ_SYS1_PLL_133M		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX8MQ_SYS1_PLL_160M		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX8MQ_SYS1_PLL_200M		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX8MQ_SYS1_PLL_266M		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX8MQ_SYS1_PLL_400M		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX8MQ_SYS1_PLL_800M		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX8MQ_SYS2_PLL_50M		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX8MQ_SYS2_PLL_100M		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX8MQ_SYS2_PLL_125M		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX8MQ_SYS2_PLL_166M		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX8MQ_SYS2_PLL_200M		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX8MQ_SYS2_PLL_250M		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX8MQ_SYS2_PLL_333M		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX8MQ_SYS2_PLL_500M		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX8MQ_SYS2_PLL_1000M		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* CCM ROOT clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* A53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX8MQ_CLK_A53_SRC		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX8MQ_CLK_A53_CG		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX8MQ_CLK_A53_DIV		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* M4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX8MQ_CLK_M4_SRC		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX8MQ_CLK_M4_CG		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX8MQ_CLK_M4_DIV		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* VPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX8MQ_CLK_VPU_SRC		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX8MQ_CLK_VPU_CG		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX8MQ_CLK_VPU_DIV		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* GPU CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX8MQ_CLK_GPU_CORE_SRC		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX8MQ_CLK_GPU_CORE_CG		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX8MQ_CLK_GPU_CORE_DIV		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* GPU SHADER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX8MQ_CLK_GPU_SHADER_SRC	100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX8MQ_CLK_GPU_SHADER_CG	101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX8MQ_CLK_GPU_SHADER_DIV	102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* BUS TYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* MAIN AXI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX8MQ_CLK_MAIN_AXI		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* ENET AXI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX8MQ_CLK_ENET_AXI		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* NAND_USDHC_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX8MQ_CLK_NAND_USDHC_BUS	105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* VPU BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX8MQ_CLK_VPU_BUS		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* DISP_AXI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX8MQ_CLK_DISP_AXI		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* DISP APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX8MQ_CLK_DISP_APB		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* DISP RTRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX8MQ_CLK_DISP_RTRM		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* USB_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX8MQ_CLK_USB_BUS		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* GPU_AXI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX8MQ_CLK_GPU_AXI		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* GPU_AHB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX8MQ_CLK_GPU_AHB		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* NOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX8MQ_CLK_NOC			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* NOC_APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX8MQ_CLK_NOC_APB		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* AHB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX8MQ_CLK_AHB			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* AUDIO AHB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX8MQ_CLK_AUDIO_AHB		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* DRAM_ALT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX8MQ_CLK_DRAM_ALT		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* DRAM APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX8MQ_CLK_DRAM_APB		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* VPU_G1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX8MQ_CLK_VPU_G1		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* VPU_G2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX8MQ_CLK_VPU_G2		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* DISP_DTRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX8MQ_CLK_DISP_DTRC		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* DISP_DC8000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX8MQ_CLK_DISP_DC8000		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* PCIE_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX8MQ_CLK_PCIE1_CTRL		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* PCIE_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX8MQ_CLK_PCIE1_PHY		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* PCIE_AUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX8MQ_CLK_PCIE1_AUX		126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* DC_PIXEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX8MQ_CLK_DC_PIXEL		127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* LCDIF_PIXEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX8MQ_CLK_LCDIF_PIXEL		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* SAI1~6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX8MQ_CLK_SAI1			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX8MQ_CLK_SAI2			130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX8MQ_CLK_SAI3			131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX8MQ_CLK_SAI4			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX8MQ_CLK_SAI5			133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX8MQ_CLK_SAI6			134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* SPDIF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX8MQ_CLK_SPDIF1		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* SPDIF2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX8MQ_CLK_SPDIF2		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* ENET_REF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX8MQ_CLK_ENET_REF		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* ENET_TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX8MQ_CLK_ENET_TIMER		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* ENET_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX8MQ_CLK_ENET_PHY_REF		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX8MQ_CLK_NAND			140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX8MQ_CLK_QSPI			141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* USDHC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX8MQ_CLK_USDHC1		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* USDHC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX8MQ_CLK_USDHC2		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* I2C1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX8MQ_CLK_I2C1			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* I2C2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX8MQ_CLK_I2C2			145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* I2C3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX8MQ_CLK_I2C3			146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* I2C4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMX8MQ_CLK_I2C4			147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX8MQ_CLK_UART1		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX8MQ_CLK_UART2		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* UART3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX8MQ_CLK_UART3		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* UART4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMX8MQ_CLK_UART4		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* USB_CORE_REF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX8MQ_CLK_USB_CORE_REF		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* USB_PHY_REF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX8MQ_CLK_USB_PHY_REF		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* ECSPI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IMX8MQ_CLK_ECSPI1		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* ECSPI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX8MQ_CLK_ECSPI2		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* PWM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX8MQ_CLK_PWM1			156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* PWM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX8MQ_CLK_PWM2			157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* PWM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX8MQ_CLK_PWM3			158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* PWM4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX8MQ_CLK_PWM4			159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* GPT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IMX8MQ_CLK_GPT1			160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* WDOG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IMX8MQ_CLK_WDOG			161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* WRCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMX8MQ_CLK_WRCLK		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* DSI_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX8MQ_CLK_DSI_CORE		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* DSI_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX8MQ_CLK_DSI_PHY_REF		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* DSI_DBI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IMX8MQ_CLK_DSI_DBI		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*DSI_ESC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IMX8MQ_CLK_DSI_ESC		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* CSI1_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IMX8MQ_CLK_CSI1_CORE		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* CSI1_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IMX8MQ_CLK_CSI1_PHY_REF		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* CSI_ESC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IMX8MQ_CLK_CSI1_ESC		169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* CSI2_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IMX8MQ_CLK_CSI2_CORE		170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* CSI2_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IMX8MQ_CLK_CSI2_PHY_REF		171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* CSI2_ESC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IMX8MQ_CLK_CSI2_ESC		172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* PCIE2_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IMX8MQ_CLK_PCIE2_CTRL		173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* PCIE2_PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IMX8MQ_CLK_PCIE2_PHY		174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* PCIE2_AUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IMX8MQ_CLK_PCIE2_AUX		175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* ECSPI3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IMX8MQ_CLK_ECSPI3		176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* CCGR clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IMX8MQ_CLK_A53_ROOT			177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IMX8MQ_CLK_DRAM_ROOT			178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IMX8MQ_CLK_ECSPI1_ROOT			179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IMX8MQ_CLK_ECSPI2_ROOT			180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IMX8MQ_CLK_ECSPI3_ROOT			181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IMX8MQ_CLK_ENET1_ROOT			182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IMX8MQ_CLK_GPT1_ROOT			183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IMX8MQ_CLK_I2C1_ROOT			184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IMX8MQ_CLK_I2C2_ROOT			185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IMX8MQ_CLK_I2C3_ROOT			186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IMX8MQ_CLK_I2C4_ROOT			187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IMX8MQ_CLK_M4_ROOT			188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IMX8MQ_CLK_PCIE1_ROOT			189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IMX8MQ_CLK_PCIE2_ROOT			190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IMX8MQ_CLK_PWM1_ROOT			191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IMX8MQ_CLK_PWM2_ROOT			192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IMX8MQ_CLK_PWM3_ROOT			193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IMX8MQ_CLK_PWM4_ROOT			194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IMX8MQ_CLK_QSPI_ROOT			195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IMX8MQ_CLK_SAI1_ROOT			196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IMX8MQ_CLK_SAI2_ROOT			197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IMX8MQ_CLK_SAI3_ROOT			198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IMX8MQ_CLK_SAI4_ROOT			199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IMX8MQ_CLK_SAI5_ROOT			200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IMX8MQ_CLK_SAI6_ROOT			201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IMX8MQ_CLK_UART1_ROOT			202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IMX8MQ_CLK_UART2_ROOT			203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IMX8MQ_CLK_UART3_ROOT			204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IMX8MQ_CLK_UART4_ROOT			205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IMX8MQ_CLK_USB1_CTRL_ROOT		206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IMX8MQ_CLK_USB2_CTRL_ROOT		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IMX8MQ_CLK_USB1_PHY_ROOT		208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IMX8MQ_CLK_USB2_PHY_ROOT		209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IMX8MQ_CLK_USDHC1_ROOT			210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IMX8MQ_CLK_USDHC2_ROOT			211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IMX8MQ_CLK_WDOG1_ROOT			212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IMX8MQ_CLK_WDOG2_ROOT			213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IMX8MQ_CLK_WDOG3_ROOT			214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IMX8MQ_CLK_GPU_ROOT			215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IMX8MQ_CLK_HEVC_ROOT			216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IMX8MQ_CLK_AVC_ROOT			217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IMX8MQ_CLK_VP9_ROOT			218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IMX8MQ_CLK_HEVC_INTER_ROOT		219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IMX8MQ_CLK_DISP_ROOT			220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IMX8MQ_CLK_HDMI_ROOT			221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IMX8MQ_CLK_HDMI_PHY_ROOT		222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IMX8MQ_CLK_VPU_DEC_ROOT			223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IMX8MQ_CLK_CSI1_ROOT			224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IMX8MQ_CLK_CSI2_ROOT			225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IMX8MQ_CLK_RAWNAND_ROOT			226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IMX8MQ_CLK_SDMA1_ROOT			227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IMX8MQ_CLK_SDMA2_ROOT			228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IMX8MQ_CLK_VPU_G1_ROOT			229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IMX8MQ_CLK_VPU_G2_ROOT			230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* SCCG PLL GATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IMX8MQ_SYS1_PLL_OUT			231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IMX8MQ_SYS2_PLL_OUT			232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IMX8MQ_SYS3_PLL_OUT			233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IMX8MQ_DRAM_PLL_OUT			234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IMX8MQ_GPT_3M_CLK			235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IMX8MQ_CLK_IPG_ROOT			236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define IMX8MQ_CLK_IPG_AUDIO_ROOT		237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define IMX8MQ_CLK_SAI1_IPG			238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IMX8MQ_CLK_SAI2_IPG			239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IMX8MQ_CLK_SAI3_IPG			240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define IMX8MQ_CLK_SAI4_IPG			241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IMX8MQ_CLK_SAI5_IPG			242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define IMX8MQ_CLK_SAI6_IPG			243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* DSI AHB/IPG clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* rxesc clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IMX8MQ_CLK_DSI_AHB			244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* txesc clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define IMX8MQ_CLK_DSI_IPG_DIV                  245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define IMX8MQ_CLK_TMU_ROOT			246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Display root clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define IMX8MQ_CLK_DISP_AXI_ROOT		247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define IMX8MQ_CLK_DISP_APB_ROOT		248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define IMX8MQ_CLK_DISP_RTRM_ROOT		249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IMX8MQ_CLK_OCOTP_ROOT			250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IMX8MQ_CLK_DRAM_ALT_ROOT		251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IMX8MQ_CLK_DRAM_CORE			252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define IMX8MQ_CLK_MU_ROOT			253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IMX8MQ_VIDEO2_PLL_OUT			254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IMX8MQ_CLK_CLKO2			255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK	256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define IMX8MQ_CLK_CLKO1			257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define IMX8MQ_CLK_ARM				258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IMX8MQ_CLK_GPIO1_ROOT			259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IMX8MQ_CLK_GPIO2_ROOT			260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define IMX8MQ_CLK_GPIO3_ROOT			261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define IMX8MQ_CLK_GPIO4_ROOT			262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define IMX8MQ_CLK_GPIO5_ROOT			263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define IMX8MQ_CLK_SNVS_ROOT			264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define IMX8MQ_CLK_GIC				265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define IMX8MQ_VIDEO2_PLL1_REF_SEL		266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define IMX8MQ_CLK_GPU_CORE			285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define IMX8MQ_CLK_GPU_SHADER			286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define IMX8MQ_CLK_M4_CORE			287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define IMX8MQ_CLK_VPU_CORE			288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define IMX8MQ_CLK_A53_CORE			289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define IMX8MQ_CLK_END				290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */