^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DT_BINDINGS_CLOCK_IMX8MP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DT_BINDINGS_CLOCK_IMX8MP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define IMX8MP_CLK_DUMMY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IMX8MP_CLK_32K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX8MP_CLK_24M 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX8MP_OSC_HDMI_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX8MP_CLK_EXT1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX8MP_CLK_EXT2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX8MP_CLK_EXT3 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX8MP_CLK_EXT4 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX8MP_AUDIO_PLL1_REF_SEL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX8MP_AUDIO_PLL2_REF_SEL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX8MP_VIDEO_PLL1_REF_SEL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX8MP_DRAM_PLL_REF_SEL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX8MP_GPU_PLL_REF_SEL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX8MP_VPU_PLL_REF_SEL 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX8MP_ARM_PLL_REF_SEL 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX8MP_SYS_PLL1_REF_SEL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX8MP_SYS_PLL2_REF_SEL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX8MP_SYS_PLL3_REF_SEL 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX8MP_AUDIO_PLL1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX8MP_AUDIO_PLL2 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX8MP_VIDEO_PLL1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX8MP_DRAM_PLL 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX8MP_GPU_PLL 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX8MP_VPU_PLL 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX8MP_ARM_PLL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX8MP_SYS_PLL1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX8MP_SYS_PLL2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX8MP_SYS_PLL3 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX8MP_AUDIO_PLL1_BYPASS 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX8MP_AUDIO_PLL2_BYPASS 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX8MP_VIDEO_PLL1_BYPASS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX8MP_DRAM_PLL_BYPASS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX8MP_GPU_PLL_BYPASS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX8MP_VPU_PLL_BYPASS 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX8MP_ARM_PLL_BYPASS 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX8MP_SYS_PLL1_BYPASS 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX8MP_SYS_PLL2_BYPASS 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX8MP_SYS_PLL3_BYPASS 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX8MP_AUDIO_PLL1_OUT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX8MP_AUDIO_PLL2_OUT 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX8MP_VIDEO_PLL1_OUT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX8MP_DRAM_PLL_OUT 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX8MP_GPU_PLL_OUT 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX8MP_VPU_PLL_OUT 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX8MP_ARM_PLL_OUT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX8MP_SYS_PLL1_OUT 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX8MP_SYS_PLL2_OUT 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX8MP_SYS_PLL3_OUT 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX8MP_SYS_PLL1_40M 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX8MP_SYS_PLL1_80M 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX8MP_SYS_PLL1_100M 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX8MP_SYS_PLL1_133M 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX8MP_SYS_PLL1_160M 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX8MP_SYS_PLL1_200M 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX8MP_SYS_PLL1_266M 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX8MP_SYS_PLL1_400M 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX8MP_SYS_PLL1_800M 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX8MP_SYS_PLL2_50M 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX8MP_SYS_PLL2_100M 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX8MP_SYS_PLL2_125M 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX8MP_SYS_PLL2_166M 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX8MP_SYS_PLL2_200M 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX8MP_SYS_PLL2_250M 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX8MP_SYS_PLL2_333M 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX8MP_SYS_PLL2_500M 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX8MP_SYS_PLL2_1000M 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX8MP_CLK_A53_SRC 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX8MP_CLK_M7_SRC 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX8MP_CLK_ML_SRC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX8MP_CLK_GPU3D_CORE_SRC 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX8MP_CLK_GPU3D_SHADER_SRC 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX8MP_CLK_GPU2D_SRC 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX8MP_CLK_AUDIO_AXI_SRC 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX8MP_CLK_HSIO_AXI_SRC 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX8MP_CLK_MEDIA_ISP_SRC 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX8MP_CLK_A53_CG 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX8MP_CLK_M4_CG 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX8MP_CLK_ML_CG 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX8MP_CLK_GPU3D_CORE_CG 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX8MP_CLK_GPU3D_SHADER_CG 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX8MP_CLK_GPU2D_CG 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX8MP_CLK_AUDIO_AXI_CG 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX8MP_CLK_HSIO_AXI_CG 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX8MP_CLK_MEDIA_ISP_CG 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX8MP_CLK_A53_DIV 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX8MP_CLK_M7_DIV 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX8MP_CLK_ML_DIV 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX8MP_CLK_GPU3D_CORE_DIV 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX8MP_CLK_GPU3D_SHADER_DIV 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX8MP_CLK_GPU2D_DIV 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX8MP_CLK_AUDIO_AXI_DIV 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX8MP_CLK_HSIO_AXI_DIV 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX8MP_CLK_MEDIA_ISP_DIV 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX8MP_CLK_MAIN_AXI 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX8MP_CLK_ENET_AXI 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX8MP_CLK_NAND_USDHC_BUS 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX8MP_CLK_VPU_BUS 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX8MP_CLK_MEDIA_AXI 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX8MP_CLK_MEDIA_APB 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX8MP_CLK_HDMI_APB 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX8MP_CLK_HDMI_AXI 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX8MP_CLK_GPU_AXI 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX8MP_CLK_GPU_AHB 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX8MP_CLK_NOC 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX8MP_CLK_NOC_IO 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX8MP_CLK_ML_AXI 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX8MP_CLK_ML_AHB 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX8MP_CLK_AHB 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX8MP_CLK_AUDIO_AHB 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX8MP_CLK_MIPI_DSI_ESC_RX 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX8MP_CLK_IPG_ROOT 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX8MP_CLK_IPG_AUDIO_ROOT 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX8MP_CLK_DRAM_ALT 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX8MP_CLK_DRAM_APB 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX8MP_CLK_VPU_G1 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX8MP_CLK_VPU_G2 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX8MP_CLK_CAN1 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX8MP_CLK_CAN2 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX8MP_CLK_MEMREPAIR 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX8MP_CLK_PCIE_PHY 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX8MP_CLK_PCIE_AUX 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX8MP_CLK_I2C5 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX8MP_CLK_I2C6 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX8MP_CLK_SAI1 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX8MP_CLK_SAI2 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX8MP_CLK_SAI3 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX8MP_CLK_SAI4 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX8MP_CLK_SAI5 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX8MP_CLK_SAI6 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX8MP_CLK_ENET_QOS 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX8MP_CLK_ENET_QOS_TIMER 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX8MP_CLK_ENET_REF 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX8MP_CLK_ENET_TIMER 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX8MP_CLK_ENET_PHY_REF 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX8MP_CLK_NAND 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX8MP_CLK_QSPI 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX8MP_CLK_USDHC1 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX8MP_CLK_USDHC2 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX8MP_CLK_I2C1 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX8MP_CLK_I2C2 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX8MP_CLK_I2C3 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX8MP_CLK_I2C4 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX8MP_CLK_UART1 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX8MP_CLK_UART2 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX8MP_CLK_UART3 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX8MP_CLK_UART4 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX8MP_CLK_USB_CORE_REF 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX8MP_CLK_USB_PHY_REF 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX8MP_CLK_GIC 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX8MP_CLK_ECSPI1 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX8MP_CLK_ECSPI2 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX8MP_CLK_PWM1 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX8MP_CLK_PWM2 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX8MP_CLK_PWM3 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX8MP_CLK_PWM4 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX8MP_CLK_GPT1 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX8MP_CLK_GPT2 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX8MP_CLK_GPT3 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX8MP_CLK_GPT4 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX8MP_CLK_GPT5 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX8MP_CLK_GPT6 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX8MP_CLK_TRACE 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX8MP_CLK_WDOG 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX8MP_CLK_WRCLK 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX8MP_CLK_IPP_DO_CLKO1 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX8MP_CLK_IPP_DO_CLKO2 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX8MP_CLK_HDMI_FDCC_TST 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX8MP_CLK_HDMI_24M 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX8MP_CLK_HDMI_REF_266M 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX8MP_CLK_USDHC3 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX8MP_CLK_MEDIA_CAM1_PIX 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX8MP_CLK_MEDIA_DISP1_PIX 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX8MP_CLK_MEDIA_CAM2_PIX 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX8MP_CLK_MEDIA_LDB 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX8MP_CLK_PCIE2_CTRL 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX8MP_CLK_PCIE2_PHY 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX8MP_CLK_ECSPI3 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX8MP_CLK_PDM 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX8MP_CLK_VPU_VC8000E 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX8MP_CLK_SAI7 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX8MP_CLK_GPC_ROOT 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX8MP_CLK_ANAMIX_ROOT 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX8MP_CLK_CPU_ROOT 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX8MP_CLK_CSU_ROOT 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX8MP_CLK_DEBUG_ROOT 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX8MP_CLK_DRAM1_ROOT 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX8MP_CLK_ECSPI1_ROOT 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX8MP_CLK_ECSPI2_ROOT 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX8MP_CLK_ECSPI3_ROOT 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX8MP_CLK_ENET1_ROOT 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX8MP_CLK_GPIO1_ROOT 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX8MP_CLK_GPIO2_ROOT 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX8MP_CLK_GPIO3_ROOT 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX8MP_CLK_GPIO4_ROOT 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX8MP_CLK_GPIO5_ROOT 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX8MP_CLK_GPT1_ROOT 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX8MP_CLK_GPT2_ROOT 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX8MP_CLK_GPT3_ROOT 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX8MP_CLK_GPT4_ROOT 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX8MP_CLK_GPT5_ROOT 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX8MP_CLK_GPT6_ROOT 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX8MP_CLK_HS_ROOT 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX8MP_CLK_I2C1_ROOT 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IMX8MP_CLK_I2C2_ROOT 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX8MP_CLK_I2C3_ROOT 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMX8MP_CLK_I2C4_ROOT 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX8MP_CLK_IOMUX_ROOT 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IMX8MP_CLK_IPMUX1_ROOT 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX8MP_CLK_IPMUX2_ROOT 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IMX8MP_CLK_IPMUX3_ROOT 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX8MP_CLK_MU_ROOT 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IMX8MP_CLK_OCOTP_ROOT 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX8MP_CLK_OCRAM_ROOT 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMX8MP_CLK_OCRAM_S_ROOT 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX8MP_CLK_PCIE_ROOT 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IMX8MP_CLK_PERFMON1_ROOT 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX8MP_CLK_PERFMON2_ROOT 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMX8MP_CLK_PWM1_ROOT 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX8MP_CLK_PWM2_ROOT 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMX8MP_CLK_PWM3_ROOT 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX8MP_CLK_PWM4_ROOT 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMX8MP_CLK_QOS_ROOT 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX8MP_CLK_QOS_ENET_ROOT 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMX8MP_CLK_QSPI_ROOT 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMX8MP_CLK_NAND_ROOT 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX8MP_CLK_RDC_ROOT 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IMX8MP_CLK_ROM_ROOT 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX8MP_CLK_I2C5_ROOT 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IMX8MP_CLK_I2C6_ROOT 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX8MP_CLK_CAN1_ROOT 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IMX8MP_CLK_CAN2_ROOT 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMX8MP_CLK_SCTR_ROOT 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMX8MP_CLK_SDMA1_ROOT 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX8MP_CLK_ENET_QOS_ROOT 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IMX8MP_CLK_SEC_DEBUG_ROOT 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX8MP_CLK_SEMA1_ROOT 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IMX8MP_CLK_SEMA2_ROOT 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IMX8MP_CLK_IRQ_STEER_ROOT 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IMX8MP_CLK_SIM_ENET_ROOT 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX8MP_CLK_SIM_M_ROOT 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMX8MP_CLK_SIM_MAIN_ROOT 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX8MP_CLK_SIM_S_ROOT 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IMX8MP_CLK_SIM_WAKEUP_ROOT 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX8MP_CLK_GPU2D_ROOT 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IMX8MP_CLK_GPU3D_ROOT 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX8MP_CLK_SNVS_ROOT 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IMX8MP_CLK_TRACE_ROOT 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX8MP_CLK_UART1_ROOT 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IMX8MP_CLK_UART2_ROOT 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IMX8MP_CLK_UART3_ROOT 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IMX8MP_CLK_UART4_ROOT 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IMX8MP_CLK_USB_ROOT 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IMX8MP_CLK_USB_PHY_ROOT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMX8MP_CLK_USDHC1_ROOT 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IMX8MP_CLK_USDHC2_ROOT 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX8MP_CLK_WDOG1_ROOT 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMX8MP_CLK_WDOG2_ROOT 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX8MP_CLK_WDOG3_ROOT 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMX8MP_CLK_VPU_G1_ROOT 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IMX8MP_CLK_GPU_ROOT 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IMX8MP_CLK_NOC_WRAPPER_ROOT 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IMX8MP_CLK_VPU_VC8KE_ROOT 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IMX8MP_CLK_VPU_G2_ROOT 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IMX8MP_CLK_NPU_ROOT 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IMX8MP_CLK_HSIO_ROOT 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IMX8MP_CLK_MEDIA_APB_ROOT 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IMX8MP_CLK_MEDIA_AXI_ROOT 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IMX8MP_CLK_MEDIA_ISP_ROOT 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IMX8MP_CLK_USDHC3_ROOT 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IMX8MP_CLK_HDMI_ROOT 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IMX8MP_CLK_XTAL_ROOT 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IMX8MP_CLK_PLL_ROOT 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IMX8MP_CLK_TSENSOR_ROOT 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IMX8MP_CLK_VPU_ROOT 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IMX8MP_CLK_MRPR_ROOT 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IMX8MP_CLK_AUDIO_ROOT 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IMX8MP_CLK_DRAM_ALT_ROOT 285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IMX8MP_CLK_DRAM_CORE 286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IMX8MP_CLK_ARM 287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IMX8MP_CLK_A53_CORE 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IMX8MP_SYS_PLL1_40M_CG 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IMX8MP_SYS_PLL1_80M_CG 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IMX8MP_SYS_PLL1_100M_CG 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IMX8MP_SYS_PLL1_133M_CG 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IMX8MP_SYS_PLL1_160M_CG 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IMX8MP_SYS_PLL1_200M_CG 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IMX8MP_SYS_PLL1_266M_CG 295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IMX8MP_SYS_PLL1_400M_CG 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IMX8MP_SYS_PLL2_50M_CG 297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IMX8MP_SYS_PLL2_100M_CG 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IMX8MP_SYS_PLL2_125M_CG 299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IMX8MP_SYS_PLL2_166M_CG 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IMX8MP_SYS_PLL2_200M_CG 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IMX8MP_SYS_PLL2_250M_CG 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IMX8MP_SYS_PLL2_333M_CG 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IMX8MP_SYS_PLL2_500M_CG 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IMX8MP_CLK_M7_CORE 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IMX8MP_CLK_ML_CORE 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IMX8MP_CLK_GPU3D_CORE 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IMX8MP_CLK_GPU3D_SHADER_CORE 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IMX8MP_CLK_GPU2D_CORE 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IMX8MP_CLK_AUDIO_AXI 310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IMX8MP_CLK_HSIO_AXI 311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IMX8MP_CLK_MEDIA_ISP 312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IMX8MP_CLK_END 313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define IMX8MP_CLK_AUDIOMIX_END 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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