Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2017-2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __DT_BINDINGS_CLOCK_IMX8MM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define IMX8MM_CLK_DUMMY			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define IMX8MM_CLK_32K				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define IMX8MM_CLK_24M				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define IMX8MM_OSC_HDMI_CLK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define IMX8MM_CLK_EXT1				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define IMX8MM_CLK_EXT2				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define IMX8MM_CLK_EXT3				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IMX8MM_CLK_EXT4				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IMX8MM_AUDIO_PLL1_REF_SEL		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IMX8MM_AUDIO_PLL2_REF_SEL		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IMX8MM_VIDEO_PLL1_REF_SEL		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IMX8MM_DRAM_PLL_REF_SEL			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IMX8MM_GPU_PLL_REF_SEL			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IMX8MM_VPU_PLL_REF_SEL			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IMX8MM_ARM_PLL_REF_SEL			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IMX8MM_SYS_PLL1_REF_SEL			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IMX8MM_SYS_PLL2_REF_SEL			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IMX8MM_SYS_PLL3_REF_SEL			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IMX8MM_AUDIO_PLL1			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IMX8MM_AUDIO_PLL2			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IMX8MM_VIDEO_PLL1			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IMX8MM_DRAM_PLL				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IMX8MM_GPU_PLL				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IMX8MM_VPU_PLL				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IMX8MM_ARM_PLL				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IMX8MM_SYS_PLL1				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IMX8MM_SYS_PLL2				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IMX8MM_SYS_PLL3				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IMX8MM_AUDIO_PLL1_BYPASS		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IMX8MM_AUDIO_PLL2_BYPASS		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IMX8MM_VIDEO_PLL1_BYPASS		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IMX8MM_DRAM_PLL_BYPASS			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IMX8MM_GPU_PLL_BYPASS			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IMX8MM_VPU_PLL_BYPASS			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IMX8MM_ARM_PLL_BYPASS			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IMX8MM_SYS_PLL1_BYPASS			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IMX8MM_SYS_PLL2_BYPASS			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IMX8MM_SYS_PLL3_BYPASS			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IMX8MM_AUDIO_PLL1_OUT			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IMX8MM_AUDIO_PLL2_OUT			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IMX8MM_VIDEO_PLL1_OUT			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IMX8MM_DRAM_PLL_OUT			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IMX8MM_GPU_PLL_OUT			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IMX8MM_VPU_PLL_OUT			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IMX8MM_ARM_PLL_OUT			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IMX8MM_SYS_PLL1_OUT			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IMX8MM_SYS_PLL2_OUT			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IMX8MM_SYS_PLL3_OUT			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IMX8MM_SYS_PLL1_40M			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IMX8MM_SYS_PLL1_80M			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IMX8MM_SYS_PLL1_100M			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IMX8MM_SYS_PLL1_133M			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IMX8MM_SYS_PLL1_160M			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IMX8MM_SYS_PLL1_200M			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IMX8MM_SYS_PLL1_266M			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IMX8MM_SYS_PLL1_400M			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IMX8MM_SYS_PLL1_800M			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IMX8MM_SYS_PLL2_50M			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IMX8MM_SYS_PLL2_100M			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IMX8MM_SYS_PLL2_125M			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IMX8MM_SYS_PLL2_166M			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IMX8MM_SYS_PLL2_200M			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IMX8MM_SYS_PLL2_250M			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IMX8MM_SYS_PLL2_333M			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IMX8MM_SYS_PLL2_500M			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IMX8MM_SYS_PLL2_1000M			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IMX8MM_CLK_A53_SRC			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define IMX8MM_CLK_M4_SRC			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IMX8MM_CLK_VPU_SRC			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define IMX8MM_CLK_GPU3D_SRC			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IMX8MM_CLK_GPU2D_SRC			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define IMX8MM_CLK_A53_CG			71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IMX8MM_CLK_M4_CG			72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IMX8MM_CLK_VPU_CG			73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IMX8MM_CLK_GPU3D_CG			74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IMX8MM_CLK_GPU2D_CG			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IMX8MM_CLK_A53_DIV			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IMX8MM_CLK_M4_DIV			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IMX8MM_CLK_VPU_DIV			78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IMX8MM_CLK_GPU3D_DIV			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define IMX8MM_CLK_GPU2D_DIV			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define IMX8MM_CLK_MAIN_AXI			81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define IMX8MM_CLK_ENET_AXI			82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IMX8MM_CLK_NAND_USDHC_BUS		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IMX8MM_CLK_VPU_BUS			84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IMX8MM_CLK_DISP_AXI			85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define IMX8MM_CLK_DISP_APB			86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX8MM_CLK_DISP_RTRM			87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX8MM_CLK_USB_BUS			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX8MM_CLK_GPU_AXI			89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX8MM_CLK_GPU_AHB			90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX8MM_CLK_NOC				91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX8MM_CLK_NOC_APB			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX8MM_CLK_AHB				93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX8MM_CLK_AUDIO_AHB			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX8MM_CLK_IPG_ROOT			95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX8MM_CLK_IPG_AUDIO_ROOT		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX8MM_CLK_DRAM_ALT			97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX8MM_CLK_DRAM_APB			98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX8MM_CLK_VPU_G1			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX8MM_CLK_VPU_G2			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX8MM_CLK_DISP_DTRC			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX8MM_CLK_DISP_DC8000			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX8MM_CLK_PCIE1_CTRL			103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX8MM_CLK_PCIE1_PHY			104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX8MM_CLK_PCIE1_AUX			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX8MM_CLK_DC_PIXEL			106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX8MM_CLK_LCDIF_PIXEL			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX8MM_CLK_SAI1				108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX8MM_CLK_SAI2				109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX8MM_CLK_SAI3				110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX8MM_CLK_SAI4				111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX8MM_CLK_SAI5				112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX8MM_CLK_SAI6				113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX8MM_CLK_SPDIF1			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX8MM_CLK_SPDIF2			115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX8MM_CLK_ENET_REF			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX8MM_CLK_ENET_TIMER			117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX8MM_CLK_ENET_PHY_REF			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX8MM_CLK_NAND				119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX8MM_CLK_QSPI				120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX8MM_CLK_USDHC1			121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX8MM_CLK_USDHC2			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX8MM_CLK_I2C1				123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX8MM_CLK_I2C2				124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX8MM_CLK_I2C3				125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX8MM_CLK_I2C4				126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX8MM_CLK_UART1			127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX8MM_CLK_UART2			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX8MM_CLK_UART3			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX8MM_CLK_UART4			130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX8MM_CLK_USB_CORE_REF			131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX8MM_CLK_USB_PHY_REF			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX8MM_CLK_ECSPI1			133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX8MM_CLK_ECSPI2			134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX8MM_CLK_PWM1				135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX8MM_CLK_PWM2				136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX8MM_CLK_PWM3				137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX8MM_CLK_PWM4				138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX8MM_CLK_GPT1				139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX8MM_CLK_WDOG				140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX8MM_CLK_WRCLK			141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX8MM_CLK_DSI_CORE			142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX8MM_CLK_DSI_PHY_REF			143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX8MM_CLK_DSI_DBI			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX8MM_CLK_USDHC3			145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX8MM_CLK_CSI1_CORE			146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX8MM_CLK_CSI1_PHY_REF			147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX8MM_CLK_CSI1_ESC			148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX8MM_CLK_CSI2_CORE			149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX8MM_CLK_CSI2_PHY_REF			150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX8MM_CLK_CSI2_ESC			151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX8MM_CLK_PCIE2_CTRL			152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX8MM_CLK_PCIE2_PHY			153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX8MM_CLK_PCIE2_AUX			154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX8MM_CLK_ECSPI3			155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX8MM_CLK_PDM				156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX8MM_CLK_VPU_H1			157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX8MM_CLK_CLKO1			158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX8MM_CLK_ECSPI1_ROOT			159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX8MM_CLK_ECSPI2_ROOT			160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX8MM_CLK_ECSPI3_ROOT			161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX8MM_CLK_ENET1_ROOT			162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX8MM_CLK_GPT1_ROOT			163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX8MM_CLK_I2C1_ROOT			164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX8MM_CLK_I2C2_ROOT			165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX8MM_CLK_I2C3_ROOT			166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX8MM_CLK_I2C4_ROOT			167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX8MM_CLK_OCOTP_ROOT			168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX8MM_CLK_PCIE1_ROOT			169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX8MM_CLK_PWM1_ROOT			170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX8MM_CLK_PWM2_ROOT			171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX8MM_CLK_PWM3_ROOT			172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX8MM_CLK_PWM4_ROOT			173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX8MM_CLK_QSPI_ROOT			174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX8MM_CLK_NAND_ROOT			175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX8MM_CLK_SAI1_ROOT			176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX8MM_CLK_SAI1_IPG			177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX8MM_CLK_SAI2_ROOT			178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX8MM_CLK_SAI2_IPG			179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX8MM_CLK_SAI3_ROOT			180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX8MM_CLK_SAI3_IPG			181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX8MM_CLK_SAI4_ROOT			182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX8MM_CLK_SAI4_IPG			183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX8MM_CLK_SAI5_ROOT			184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX8MM_CLK_SAI5_IPG			185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX8MM_CLK_SAI6_ROOT			186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX8MM_CLK_SAI6_IPG			187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX8MM_CLK_UART1_ROOT			188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX8MM_CLK_UART2_ROOT			189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX8MM_CLK_UART3_ROOT			190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX8MM_CLK_UART4_ROOT			191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX8MM_CLK_USB1_CTRL_ROOT		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX8MM_CLK_GPU3D_ROOT			193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX8MM_CLK_USDHC1_ROOT			194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX8MM_CLK_USDHC2_ROOT			195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX8MM_CLK_WDOG1_ROOT			196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX8MM_CLK_WDOG2_ROOT			197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX8MM_CLK_WDOG3_ROOT			198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IMX8MM_CLK_VPU_G1_ROOT			199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX8MM_CLK_GPU_BUS_ROOT			200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMX8MM_CLK_VPU_H1_ROOT			201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX8MM_CLK_VPU_G2_ROOT			202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IMX8MM_CLK_PDM_ROOT			203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX8MM_CLK_DISP_ROOT			204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IMX8MM_CLK_DISP_AXI_ROOT		205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX8MM_CLK_DISP_APB_ROOT		206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IMX8MM_CLK_DISP_RTRM_ROOT		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX8MM_CLK_USDHC3_ROOT			208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMX8MM_CLK_TMU_ROOT			209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX8MM_CLK_VPU_DEC_ROOT			210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IMX8MM_CLK_SDMA1_ROOT			211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX8MM_CLK_SDMA2_ROOT			212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMX8MM_CLK_SDMA3_ROOT			213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX8MM_CLK_GPT_3M			214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMX8MM_CLK_ARM				215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX8MM_CLK_PDM_IPG			216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMX8MM_CLK_GPU2D_ROOT			217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX8MM_CLK_MU_ROOT			218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMX8MM_CLK_CSI1_ROOT			219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMX8MM_CLK_DRAM_CORE			220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX8MM_CLK_DRAM_ALT_ROOT		221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK	222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX8MM_CLK_GPIO1_ROOT			223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IMX8MM_CLK_GPIO2_ROOT			224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMX8MM_CLK_GPIO3_ROOT			225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMX8MM_CLK_GPIO4_ROOT			226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX8MM_CLK_GPIO5_ROOT			227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX8MM_CLK_SNVS_ROOT			228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IMX8MM_CLK_GIC				229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IMX8MM_SYS_PLL1_40M_CG			230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX8MM_SYS_PLL1_80M_CG			231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMX8MM_SYS_PLL1_100M_CG			232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX8MM_SYS_PLL1_133M_CG			233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IMX8MM_SYS_PLL1_160M_CG			234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX8MM_SYS_PLL1_200M_CG			235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IMX8MM_SYS_PLL1_266M_CG			236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX8MM_SYS_PLL1_400M_CG			237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IMX8MM_SYS_PLL2_50M_CG			238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX8MM_SYS_PLL2_100M_CG			239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IMX8MM_SYS_PLL2_125M_CG			240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IMX8MM_SYS_PLL2_166M_CG			241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IMX8MM_SYS_PLL2_200M_CG			242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IMX8MM_SYS_PLL2_250M_CG			243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IMX8MM_SYS_PLL2_333M_CG			244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMX8MM_SYS_PLL2_500M_CG			245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX8MM_CLK_M4_CORE			246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMX8MM_CLK_VPU_CORE			247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX8MM_CLK_GPU3D_CORE			248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMX8MM_CLK_GPU2D_CORE			249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IMX8MM_CLK_CLKO2			250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IMX8MM_CLK_A53_CORE			251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IMX8MM_CLK_END				252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #endif