^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Dong Aisheng <aisheng.dong@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __DT_BINDINGS_CLOCK_IMX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __DT_BINDINGS_CLOCK_IMX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* SCU Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX_CLK_DUMMY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX_A35_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* LSIO SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX_LSIO_MEM_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX_LSIO_BUS_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX_LSIO_PWM0_CLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX_LSIO_PWM1_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX_LSIO_PWM2_CLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX_LSIO_PWM3_CLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX_LSIO_PWM4_CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX_LSIO_PWM5_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX_LSIO_PWM6_CLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX_LSIO_PWM7_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX_LSIO_GPT0_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX_LSIO_GPT1_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX_LSIO_GPT2_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX_LSIO_GPT3_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX_LSIO_GPT4_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX_LSIO_FSPI0_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX_LSIO_FSPI1_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Connectivity SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX_CONN_AXI_CLK_ROOT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX_CONN_AHB_CLK_ROOT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX_CONN_IPG_CLK_ROOT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX_CONN_SDHC0_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX_CONN_SDHC1_CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX_CONN_SDHC2_CLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX_CONN_ENET0_ROOT_CLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX_CONN_ENET0_BYPASS_CLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX_CONN_ENET0_RGMII_CLK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX_CONN_ENET1_ROOT_CLK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX_CONN_ENET1_BYPASS_CLK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX_CONN_ENET1_RGMII_CLK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX_CONN_GPMI_BCH_IO_CLK 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX_CONN_GPMI_BCH_CLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX_CONN_USB2_ACLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX_CONN_USB2_BUS_CLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX_CONN_USB2_LPM_CLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* HSIO SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX_HSIO_AXI_CLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX_HSIO_PER_CLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Display controller SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX_DC_AXI_EXT_CLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX_DC_AXI_INT_CLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX_DC_CFG_CLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX_DC0_PLL0_CLK 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX_DC0_PLL1_CLK 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX_DC0_DISP0_CLK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX_DC0_DISP1_CLK 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* MIPI-LVDS SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX_MIPI_IPG_CLK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX_MIPI0_PIXEL_CLK 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX_MIPI0_BYPASS_CLK 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX_MIPI0_LVDS_PIXEL_CLK 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX_MIPI0_LVDS_BYPASS_CLK 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX_MIPI0_LVDS_PHY_CLK 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX_MIPI0_I2C0_CLK 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX_MIPI0_I2C1_CLK 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX_MIPI0_PWM0_CLK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX_MIPI1_PIXEL_CLK 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX_MIPI1_BYPASS_CLK 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX_MIPI1_LVDS_PIXEL_CLK 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX_MIPI1_LVDS_BYPASS_CLK 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX_MIPI1_LVDS_PHY_CLK 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX_MIPI1_I2C0_CLK 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX_MIPI1_I2C1_CLK 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX_MIPI1_PWM0_CLK 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* IMG SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX_IMG_AXI_CLK 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX_IMG_IPG_CLK 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX_IMG_PXL_CLK 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* MIPI-CSI SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX_CSI0_CORE_CLK 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX_CSI0_ESC_CLK 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX_CSI0_PWM0_CLK 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX_CSI0_I2C0_CLK 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* PARALLER CSI SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX_PARALLEL_CSI_DPLL_CLK 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX_PARALLEL_CSI_PIXEL_CLK 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX_PARALLEL_CSI_MCLK_CLK 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* VPU SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX_VPU_ENC_CLK 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX_VPU_DEC_CLK 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* GPU SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX_GPU0_CORE_CLK 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX_GPU0_SHADER_CLK 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* ADMA SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX_ADMA_IPG_CLK_ROOT 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX_ADMA_UART0_CLK 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX_ADMA_UART1_CLK 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX_ADMA_UART2_CLK 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX_ADMA_UART3_CLK 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX_ADMA_SPI0_CLK 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX_ADMA_SPI1_CLK 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX_ADMA_SPI2_CLK 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX_ADMA_SPI3_CLK 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX_ADMA_CAN0_CLK 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX_ADMA_CAN1_CLK 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX_ADMA_CAN2_CLK 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX_ADMA_I2C0_CLK 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX_ADMA_I2C1_CLK 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX_ADMA_I2C2_CLK 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX_ADMA_I2C3_CLK 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX_ADMA_FTM0_CLK 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX_ADMA_FTM1_CLK 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX_ADMA_ADC0_CLK 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX_ADMA_PWM_CLK 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX_ADMA_LCD_CLK 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX_SCU_CLK_END 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* LPCG clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* LSIO SS LPCG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX_LSIO_LPCG_PWM0_IPG_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX_LSIO_LPCG_PWM1_IPG_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX_LSIO_LPCG_PWM2_IPG_CLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX_LSIO_LPCG_PWM3_IPG_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX_LSIO_LPCG_PWM4_IPG_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX_LSIO_LPCG_PWM5_IPG_CLK 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX_LSIO_LPCG_PWM6_IPG_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX_LSIO_LPCG_PWM7_IPG_CLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX_LSIO_LPCG_GPT0_IPG_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX_LSIO_LPCG_GPT1_IPG_CLK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX_LSIO_LPCG_GPT2_IPG_CLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX_LSIO_LPCG_GPT3_IPG_CLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX_LSIO_LPCG_GPT4_IPG_CLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX_LSIO_LPCG_FSPI0_HCLK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX_LSIO_LPCG_FSPI1_HCLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX_LSIO_LPCG_CLK_END 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Connectivity SS LPCG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX_CONN_LPCG_SDHC0_IPG_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMX_CONN_LPCG_SDHC0_PER_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX_CONN_LPCG_SDHC0_HCLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IMX_CONN_LPCG_SDHC1_IPG_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX_CONN_LPCG_SDHC1_PER_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IMX_CONN_LPCG_SDHC1_HCLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX_CONN_LPCG_SDHC2_IPG_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IMX_CONN_LPCG_SDHC2_PER_CLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX_CONN_LPCG_SDHC2_HCLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMX_CONN_LPCG_GPMI_APB_CLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX_CONN_LPCG_GPMI_BCH_CLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMX_CONN_LPCG_APBHDMA_CLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX_CONN_LPCG_ENET0_ROOT_CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMX_CONN_LPCG_ENET0_TX_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX_CONN_LPCG_ENET0_AHB_CLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX_CONN_LPCG_ENET0_IPG_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMX_CONN_LPCG_ENET1_ROOT_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMX_CONN_LPCG_ENET1_TX_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX_CONN_LPCG_ENET1_AHB_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX_CONN_LPCG_ENET1_IPG_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX_CONN_LPCG_CLK_END 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* ADMA SS LPCG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMX_ADMA_LPCG_UART0_IPG_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX_ADMA_LPCG_UART0_BAUD_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IMX_ADMA_LPCG_UART1_IPG_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX_ADMA_LPCG_UART1_BAUD_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IMX_ADMA_LPCG_UART2_IPG_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IMX_ADMA_LPCG_UART2_BAUD_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IMX_ADMA_LPCG_UART3_IPG_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX_ADMA_LPCG_UART3_BAUD_CLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMX_ADMA_LPCG_SPI0_IPG_CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX_ADMA_LPCG_SPI1_IPG_CLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IMX_ADMA_LPCG_SPI2_IPG_CLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX_ADMA_LPCG_SPI3_IPG_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IMX_ADMA_LPCG_SPI0_CLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX_ADMA_LPCG_SPI1_CLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IMX_ADMA_LPCG_SPI2_CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX_ADMA_LPCG_SPI3_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IMX_ADMA_LPCG_CAN0_IPG_CLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IMX_ADMA_LPCG_CAN1_IPG_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IMX_ADMA_LPCG_CAN2_IPG_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX_ADMA_LPCG_I2C0_CLK 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMX_ADMA_LPCG_I2C1_CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IMX_ADMA_LPCG_I2C2_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IMX_ADMA_LPCG_I2C3_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IMX_ADMA_LPCG_I2C0_IPG_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IMX_ADMA_LPCG_I2C1_IPG_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IMX_ADMA_LPCG_I2C2_IPG_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IMX_ADMA_LPCG_I2C3_IPG_CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IMX_ADMA_LPCG_FTM0_CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IMX_ADMA_LPCG_FTM1_CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IMX_ADMA_LPCG_FTM0_IPG_CLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IMX_ADMA_LPCG_FTM1_IPG_CLK 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IMX_ADMA_LPCG_PWM_HI_CLK 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IMX_ADMA_LPCG_PWM_IPG_CLK 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IMX_ADMA_LPCG_LCD_PIX_CLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IMX_ADMA_LPCG_LCD_APB_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IMX_ADMA_LPCG_DSP_ADB_CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IMX_ADMA_LPCG_DSP_IPG_CLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IMX_ADMA_LPCG_DSP_CORE_CLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IMX_ADMA_LPCG_CLK_END 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif /* __DT_BINDINGS_CLOCK_IMX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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