^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017~2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DT_BINDINGS_CLOCK_IMX7ULP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* SCG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX7ULP_CLK_DUMMY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX7ULP_CLK_ROSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX7ULP_CLK_SOSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX7ULP_CLK_FIRC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX7ULP_CLK_SPLL_PRE_SEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX7ULP_CLK_SPLL_PRE_DIV 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX7ULP_CLK_SPLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX7ULP_CLK_SPLL_POST_DIV1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX7ULP_CLK_SPLL_POST_DIV2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX7ULP_CLK_SPLL_PFD0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX7ULP_CLK_SPLL_PFD1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX7ULP_CLK_SPLL_PFD2 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX7ULP_CLK_SPLL_PFD3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX7ULP_CLK_SPLL_PFD_SEL 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX7ULP_CLK_SPLL_SEL 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX7ULP_CLK_APLL_PRE_SEL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX7ULP_CLK_APLL_PRE_DIV 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX7ULP_CLK_APLL 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX7ULP_CLK_APLL_POST_DIV1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX7ULP_CLK_APLL_POST_DIV2 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX7ULP_CLK_APLL_PFD0 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX7ULP_CLK_APLL_PFD1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX7ULP_CLK_APLL_PFD2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX7ULP_CLK_APLL_PFD3 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX7ULP_CLK_APLL_PFD_SEL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX7ULP_CLK_APLL_SEL 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX7ULP_CLK_UPLL 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX7ULP_CLK_SYS_SEL 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX7ULP_CLK_CORE_DIV 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX7ULP_CLK_BUS_DIV 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX7ULP_CLK_PLAT_DIV 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX7ULP_CLK_DDR_SEL 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX7ULP_CLK_DDR_DIV 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX7ULP_CLK_NIC_SEL 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX7ULP_CLK_NIC0_DIV 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX7ULP_CLK_GPU_DIV 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX7ULP_CLK_NIC1_DIV 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX7ULP_CLK_NIC1_BUS_DIV 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX7ULP_CLK_NIC1_EXT_DIV 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX7ULP_CLK_MIPI_PLL 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX7ULP_CLK_SIRC 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX7ULP_CLK_SOSC_BUS_CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX7ULP_CLK_FIRC_BUS_CLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX7ULP_CLK_SPLL_BUS_CLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX7ULP_CLK_HSRUN_SYS_SEL 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX7ULP_CLK_HSRUN_CORE_DIV 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX7ULP_CLK_CORE 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX7ULP_CLK_HSRUN_CORE 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX7ULP_CLK_SCG1_END 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* PCC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX7ULP_CLK_DMA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX7ULP_CLK_RGPIO2P1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX7ULP_CLK_FLEXBUS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX7ULP_CLK_SEMA42_1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX7ULP_CLK_DMA_MUX1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX7ULP_CLK_CAAM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX7ULP_CLK_LPTPM4 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX7ULP_CLK_LPTPM5 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX7ULP_CLK_LPIT1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX7ULP_CLK_LPSPI2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX7ULP_CLK_LPSPI3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX7ULP_CLK_LPI2C4 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX7ULP_CLK_LPI2C5 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX7ULP_CLK_LPUART4 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX7ULP_CLK_LPUART5 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX7ULP_CLK_FLEXIO1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX7ULP_CLK_USB0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX7ULP_CLK_USB1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX7ULP_CLK_USB_PHY 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX7ULP_CLK_USB_PL301 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX7ULP_CLK_USDHC0 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX7ULP_CLK_USDHC1 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX7ULP_CLK_WDG1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX7ULP_CLK_WDG2 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX7ULP_CLK_PCC2_END 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* PCC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX7ULP_CLK_LPTPM6 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX7ULP_CLK_LPTPM7 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX7ULP_CLK_LPI2C6 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX7ULP_CLK_LPI2C7 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX7ULP_CLK_LPUART6 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX7ULP_CLK_LPUART7 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX7ULP_CLK_VIU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX7ULP_CLK_DSI 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX7ULP_CLK_LCDIF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX7ULP_CLK_MMDC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX7ULP_CLK_PCTLC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX7ULP_CLK_PCTLD 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX7ULP_CLK_PCTLE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX7ULP_CLK_PCTLF 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX7ULP_CLK_GPU3D 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX7ULP_CLK_GPU2D 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX7ULP_CLK_PCC3_END 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* SMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX7ULP_CLK_ARM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX7ULP_CLK_SMC1_END 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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