Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __DT_BINDINGS_CLOCK_IMX7D_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __DT_BINDINGS_CLOCK_IMX7D_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define IMX7D_OSC_24M_CLK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define IMX7D_PLL_ARM_MAIN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define IMX7D_PLL_ARM_MAIN_CLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define IMX7D_PLL_ARM_MAIN_SRC		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define IMX7D_PLL_ARM_MAIN_BYPASS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define IMX7D_PLL_SYS_MAIN		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define IMX7D_PLL_SYS_MAIN_CLK		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IMX7D_PLL_SYS_MAIN_SRC		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IMX7D_PLL_SYS_MAIN_BYPASS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IMX7D_PLL_SYS_MAIN_480M		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IMX7D_PLL_SYS_MAIN_240M		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IMX7D_PLL_SYS_MAIN_120M		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IMX7D_PLL_SYS_MAIN_480M_CLK	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IMX7D_PLL_SYS_MAIN_240M_CLK	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IMX7D_PLL_SYS_MAIN_120M_CLK	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IMX7D_PLL_SYS_PFD0_392M_CLK	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IMX7D_PLL_SYS_PFD0_196M		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IMX7D_PLL_SYS_PFD0_196M_CLK	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IMX7D_PLL_SYS_PFD1_332M_CLK	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IMX7D_PLL_SYS_PFD1_166M		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IMX7D_PLL_SYS_PFD1_166M_CLK	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IMX7D_PLL_SYS_PFD2_270M_CLK	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IMX7D_PLL_SYS_PFD2_135M		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IMX7D_PLL_SYS_PFD2_135M_CLK	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IMX7D_PLL_SYS_PFD3_CLK		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IMX7D_PLL_SYS_PFD4_CLK		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IMX7D_PLL_SYS_PFD5_CLK		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IMX7D_PLL_SYS_PFD6_CLK		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IMX7D_PLL_SYS_PFD7_CLK		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IMX7D_PLL_ENET_MAIN		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IMX7D_PLL_ENET_MAIN_CLK		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IMX7D_PLL_ENET_MAIN_SRC		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IMX7D_PLL_ENET_MAIN_BYPASS	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IMX7D_PLL_ENET_MAIN_500M	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IMX7D_PLL_ENET_MAIN_250M	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IMX7D_PLL_ENET_MAIN_125M	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IMX7D_PLL_ENET_MAIN_100M	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IMX7D_PLL_ENET_MAIN_50M		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IMX7D_PLL_ENET_MAIN_40M		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IMX7D_PLL_ENET_MAIN_25M		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IMX7D_PLL_ENET_MAIN_500M_CLK	40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IMX7D_PLL_ENET_MAIN_250M_CLK	41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IMX7D_PLL_ENET_MAIN_125M_CLK	42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IMX7D_PLL_ENET_MAIN_100M_CLK	43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IMX7D_PLL_ENET_MAIN_50M_CLK	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IMX7D_PLL_ENET_MAIN_40M_CLK	45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IMX7D_PLL_ENET_MAIN_25M_CLK	46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IMX7D_PLL_DRAM_MAIN		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IMX7D_PLL_DRAM_MAIN_CLK		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IMX7D_PLL_DRAM_MAIN_SRC		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IMX7D_PLL_DRAM_MAIN_BYPASS	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IMX7D_PLL_DRAM_MAIN_533M	51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IMX7D_PLL_DRAM_MAIN_533M_CLK	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IMX7D_PLL_AUDIO_MAIN		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IMX7D_PLL_AUDIO_MAIN_CLK	54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IMX7D_PLL_AUDIO_MAIN_SRC	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IMX7D_PLL_AUDIO_MAIN_BYPASS	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IMX7D_PLL_VIDEO_MAIN_CLK	57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IMX7D_PLL_VIDEO_MAIN		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IMX7D_PLL_VIDEO_MAIN_SRC	59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IMX7D_PLL_VIDEO_MAIN_BYPASS	60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IMX7D_USB_MAIN_480M_CLK		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IMX7D_ARM_A7_ROOT_CLK		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IMX7D_ARM_A7_ROOT_SRC		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IMX7D_ARM_A7_ROOT_CG		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IMX7D_ARM_A7_ROOT_DIV		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IMX7D_ARM_M4_ROOT_CLK		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IMX7D_ARM_M4_ROOT_SRC		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IMX7D_ARM_M4_ROOT_CG		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define IMX7D_ARM_M4_ROOT_DIV		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IMX7D_ARM_M0_ROOT_CLK		70	/* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define IMX7D_ARM_M0_ROOT_SRC		71	/* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IMX7D_ARM_M0_ROOT_CG		72	/* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define IMX7D_ARM_M0_ROOT_DIV		73	/* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IMX7D_MAIN_AXI_ROOT_CLK		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IMX7D_MAIN_AXI_ROOT_SRC		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IMX7D_MAIN_AXI_ROOT_CG		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IMX7D_MAIN_AXI_ROOT_DIV		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IMX7D_DISP_AXI_ROOT_CLK		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IMX7D_DISP_AXI_ROOT_SRC		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IMX7D_DISP_AXI_ROOT_CG		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IMX7D_DISP_AXI_ROOT_DIV		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define IMX7D_ENET_AXI_ROOT_CLK		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define IMX7D_ENET_AXI_ROOT_SRC		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define IMX7D_ENET_AXI_ROOT_CG		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define IMX7D_ENET_AXI_ROOT_DIV		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define IMX7D_NAND_USDHC_BUS_ROOT_CLK	86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IMX7D_NAND_USDHC_BUS_ROOT_SRC	87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IMX7D_NAND_USDHC_BUS_ROOT_CG	88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IMX7D_NAND_USDHC_BUS_ROOT_DIV	89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define IMX7D_AHB_CHANNEL_ROOT_CLK	90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX7D_AHB_CHANNEL_ROOT_SRC	91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX7D_AHB_CHANNEL_ROOT_CG	92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX7D_AHB_CHANNEL_ROOT_DIV	93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX7D_DRAM_PHYM_ROOT_CLK	94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX7D_DRAM_PHYM_ROOT_SRC	95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX7D_DRAM_PHYM_ROOT_CG		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX7D_DRAM_PHYM_ROOT_DIV	97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX7D_DRAM_ROOT_CLK		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX7D_DRAM_ROOT_SRC		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX7D_DRAM_ROOT_CG		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX7D_DRAM_ROOT_DIV		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX7D_DRAM_PHYM_ALT_ROOT_CLK	102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX7D_DRAM_PHYM_ALT_ROOT_SRC	103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX7D_DRAM_PHYM_ALT_ROOT_CG	104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX7D_DRAM_PHYM_ALT_ROOT_DIV	105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX7D_DRAM_ALT_ROOT_CLK		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX7D_DRAM_ALT_ROOT_SRC		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX7D_DRAM_ALT_ROOT_CG		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX7D_DRAM_ALT_ROOT_DIV		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX7D_USB_HSIC_ROOT_CLK		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX7D_USB_HSIC_ROOT_SRC		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX7D_USB_HSIC_ROOT_CG		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX7D_USB_HSIC_ROOT_DIV		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX7D_PCIE_CTRL_ROOT_CLK	114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX7D_PCIE_CTRL_ROOT_SRC	115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX7D_PCIE_CTRL_ROOT_CG		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX7D_PCIE_CTRL_ROOT_DIV	117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX7D_PCIE_PHY_ROOT_CLK		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX7D_PCIE_PHY_ROOT_SRC		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX7D_PCIE_PHY_ROOT_CG		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX7D_PCIE_PHY_ROOT_DIV		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX7D_EPDC_PIXEL_ROOT_CLK	122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX7D_EPDC_PIXEL_ROOT_SRC	123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX7D_EPDC_PIXEL_ROOT_CG	124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX7D_EPDC_PIXEL_ROOT_DIV	125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX7D_LCDIF_PIXEL_ROOT_CLK	126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX7D_LCDIF_PIXEL_ROOT_SRC	127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX7D_LCDIF_PIXEL_ROOT_CG	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX7D_LCDIF_PIXEL_ROOT_DIV	129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX7D_MIPI_DSI_ROOT_CLK		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX7D_MIPI_DSI_ROOT_SRC		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX7D_MIPI_DSI_ROOT_CG		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX7D_MIPI_DSI_ROOT_DIV		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX7D_MIPI_CSI_ROOT_CLK		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX7D_MIPI_CSI_ROOT_SRC		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX7D_MIPI_CSI_ROOT_CG		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX7D_MIPI_CSI_ROOT_DIV		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX7D_MIPI_DPHY_ROOT_CLK	138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX7D_MIPI_DPHY_ROOT_SRC	139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX7D_MIPI_DPHY_ROOT_CG		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX7D_MIPI_DPHY_ROOT_DIV	141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX7D_SAI1_ROOT_CLK		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX7D_SAI1_ROOT_SRC		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX7D_SAI1_ROOT_CG		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX7D_SAI1_ROOT_DIV		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX7D_SAI2_ROOT_CLK		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX7D_SAI2_ROOT_SRC		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX7D_SAI2_ROOT_CG		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX7D_SAI2_ROOT_DIV		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX7D_SAI3_ROOT_CLK		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX7D_SAI3_ROOT_SRC		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX7D_SAI3_ROOT_CG		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX7D_SAI3_ROOT_DIV		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX7D_SPDIF_ROOT_CLK		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX7D_SPDIF_ROOT_SRC		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX7D_SPDIF_ROOT_CG		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX7D_SPDIF_ROOT_DIV		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX7D_ENET1_IPG_ROOT_CLK        158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX7D_ENET1_REF_ROOT_SRC	159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX7D_ENET1_REF_ROOT_CG		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX7D_ENET1_REF_ROOT_DIV	161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX7D_ENET1_TIME_ROOT_CLK	162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX7D_ENET1_TIME_ROOT_SRC	163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX7D_ENET1_TIME_ROOT_CG	164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX7D_ENET1_TIME_ROOT_DIV	165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX7D_ENET2_IPG_ROOT_CLK        166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX7D_ENET2_REF_ROOT_SRC	167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX7D_ENET2_REF_ROOT_CG		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX7D_ENET2_REF_ROOT_DIV	169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX7D_ENET2_TIME_ROOT_CLK	170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX7D_ENET2_TIME_ROOT_SRC	171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX7D_ENET2_TIME_ROOT_CG	172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX7D_ENET2_TIME_ROOT_DIV	173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX7D_ENET_PHY_REF_ROOT_CLK	174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX7D_ENET_PHY_REF_ROOT_SRC	175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX7D_ENET_PHY_REF_ROOT_CG	176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX7D_ENET_PHY_REF_ROOT_DIV	177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX7D_EIM_ROOT_CLK		178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX7D_EIM_ROOT_SRC		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX7D_EIM_ROOT_CG		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX7D_EIM_ROOT_DIV		181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX7D_NAND_ROOT_CLK		182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX7D_NAND_ROOT_SRC		183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX7D_NAND_ROOT_CG		184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX7D_NAND_ROOT_DIV		185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX7D_QSPI_ROOT_CLK		186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX7D_QSPI_ROOT_SRC		187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX7D_QSPI_ROOT_CG		188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX7D_QSPI_ROOT_DIV		189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX7D_USDHC1_ROOT_CLK		190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX7D_USDHC1_ROOT_SRC		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX7D_USDHC1_ROOT_CG		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX7D_USDHC1_ROOT_DIV		193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX7D_USDHC2_ROOT_CLK		194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX7D_USDHC2_ROOT_SRC		195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX7D_USDHC2_ROOT_CG		196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX7D_USDHC2_ROOT_DIV		197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX7D_USDHC3_ROOT_CLK		198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX7D_USDHC3_ROOT_SRC		199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX7D_USDHC3_ROOT_CG		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX7D_USDHC3_ROOT_DIV		201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX7D_CAN1_ROOT_CLK		202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX7D_CAN1_ROOT_SRC		203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX7D_CAN1_ROOT_CG		204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX7D_CAN1_ROOT_DIV		205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IMX7D_CAN2_ROOT_CLK		206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX7D_CAN2_ROOT_SRC		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMX7D_CAN2_ROOT_CG		208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX7D_CAN2_ROOT_DIV		209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IMX7D_I2C1_ROOT_CLK		210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX7D_I2C1_ROOT_SRC		211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IMX7D_I2C1_ROOT_CG		212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX7D_I2C1_ROOT_DIV		213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IMX7D_I2C2_ROOT_CLK		214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX7D_I2C2_ROOT_SRC		215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMX7D_I2C2_ROOT_CG		216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX7D_I2C2_ROOT_DIV		217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IMX7D_I2C3_ROOT_CLK		218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX7D_I2C3_ROOT_SRC		219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMX7D_I2C3_ROOT_CG		220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX7D_I2C3_ROOT_DIV		221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMX7D_I2C4_ROOT_CLK		222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX7D_I2C4_ROOT_SRC		223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMX7D_I2C4_ROOT_CG		224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX7D_I2C4_ROOT_DIV		225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMX7D_UART1_ROOT_CLK		226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMX7D_UART1_ROOT_SRC		227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMX7D_UART1_ROOT_CG		228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX7D_UART1_ROOT_DIV		229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IMX7D_UART2_ROOT_CLK		230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX7D_UART2_ROOT_SRC		231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IMX7D_UART2_ROOT_CG		232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX7D_UART2_ROOT_DIV		233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IMX7D_UART3_ROOT_CLK		234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMX7D_UART3_ROOT_SRC		235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMX7D_UART3_ROOT_CG		236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX7D_UART3_ROOT_DIV		237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IMX7D_UART4_ROOT_CLK		238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX7D_UART4_ROOT_SRC		239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IMX7D_UART4_ROOT_CG		240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IMX7D_UART4_ROOT_DIV		241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IMX7D_UART5_ROOT_CLK		242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX7D_UART5_ROOT_SRC		243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMX7D_UART5_ROOT_CG		244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX7D_UART5_ROOT_DIV		245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IMX7D_UART6_ROOT_CLK		246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX7D_UART6_ROOT_SRC		247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IMX7D_UART6_ROOT_CG		248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX7D_UART6_ROOT_DIV		249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IMX7D_UART7_ROOT_CLK		250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX7D_UART7_ROOT_SRC		251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IMX7D_UART7_ROOT_CG		252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IMX7D_UART7_ROOT_DIV		253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IMX7D_ECSPI1_ROOT_CLK		254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IMX7D_ECSPI1_ROOT_SRC		255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IMX7D_ECSPI1_ROOT_CG		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMX7D_ECSPI1_ROOT_DIV		257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IMX7D_ECSPI2_ROOT_CLK		258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX7D_ECSPI2_ROOT_SRC		259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMX7D_ECSPI2_ROOT_CG		260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX7D_ECSPI2_ROOT_DIV		261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMX7D_ECSPI3_ROOT_CLK		262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IMX7D_ECSPI3_ROOT_SRC		263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IMX7D_ECSPI3_ROOT_CG		264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IMX7D_ECSPI3_ROOT_DIV		265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IMX7D_ECSPI4_ROOT_CLK		266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IMX7D_ECSPI4_ROOT_SRC		267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IMX7D_ECSPI4_ROOT_CG		268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IMX7D_ECSPI4_ROOT_DIV		269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IMX7D_PWM1_ROOT_CLK		270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IMX7D_PWM1_ROOT_SRC		271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IMX7D_PWM1_ROOT_CG		272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IMX7D_PWM1_ROOT_DIV		273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IMX7D_PWM2_ROOT_CLK		274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IMX7D_PWM2_ROOT_SRC		275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IMX7D_PWM2_ROOT_CG		276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IMX7D_PWM2_ROOT_DIV		277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IMX7D_PWM3_ROOT_CLK		278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IMX7D_PWM3_ROOT_SRC		279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IMX7D_PWM3_ROOT_CG		280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IMX7D_PWM3_ROOT_DIV		281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IMX7D_PWM4_ROOT_CLK		282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IMX7D_PWM4_ROOT_SRC		283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IMX7D_PWM4_ROOT_CG		284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IMX7D_PWM4_ROOT_DIV		285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IMX7D_FLEXTIMER1_ROOT_CLK	286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IMX7D_FLEXTIMER1_ROOT_SRC	287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IMX7D_FLEXTIMER1_ROOT_CG	288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IMX7D_FLEXTIMER1_ROOT_DIV	289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IMX7D_FLEXTIMER2_ROOT_CLK	290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IMX7D_FLEXTIMER2_ROOT_SRC	291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IMX7D_FLEXTIMER2_ROOT_CG	292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IMX7D_FLEXTIMER2_ROOT_DIV	293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IMX7D_SIM1_ROOT_CLK		294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IMX7D_SIM1_ROOT_SRC		295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IMX7D_SIM1_ROOT_CG		296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IMX7D_SIM1_ROOT_DIV		297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IMX7D_SIM2_ROOT_CLK		298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IMX7D_SIM2_ROOT_SRC		299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IMX7D_SIM2_ROOT_CG		300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IMX7D_SIM2_ROOT_DIV		301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IMX7D_GPT1_ROOT_CLK		302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IMX7D_GPT1_ROOT_SRC		303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IMX7D_GPT1_ROOT_CG		304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IMX7D_GPT1_ROOT_DIV		305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IMX7D_GPT2_ROOT_CLK		306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IMX7D_GPT2_ROOT_SRC		307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IMX7D_GPT2_ROOT_CG		308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IMX7D_GPT2_ROOT_DIV		309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IMX7D_GPT3_ROOT_CLK		310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IMX7D_GPT3_ROOT_SRC		311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IMX7D_GPT3_ROOT_CG		312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IMX7D_GPT3_ROOT_DIV		313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IMX7D_GPT4_ROOT_CLK		314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IMX7D_GPT4_ROOT_SRC		315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IMX7D_GPT4_ROOT_CG		316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IMX7D_GPT4_ROOT_DIV		317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IMX7D_TRACE_ROOT_CLK		318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IMX7D_TRACE_ROOT_SRC		319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IMX7D_TRACE_ROOT_CG		320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IMX7D_TRACE_ROOT_DIV		321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IMX7D_WDOG1_ROOT_CLK		322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IMX7D_WDOG_ROOT_SRC		323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IMX7D_WDOG_ROOT_CG		324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IMX7D_WDOG_ROOT_DIV		325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IMX7D_CSI_MCLK_ROOT_CLK		326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IMX7D_CSI_MCLK_ROOT_SRC		327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IMX7D_CSI_MCLK_ROOT_CG		328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IMX7D_CSI_MCLK_ROOT_DIV		329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IMX7D_AUDIO_MCLK_ROOT_CLK	330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IMX7D_AUDIO_MCLK_ROOT_SRC	331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IMX7D_AUDIO_MCLK_ROOT_CG	332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IMX7D_AUDIO_MCLK_ROOT_DIV	333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IMX7D_WRCLK_ROOT_CLK		334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IMX7D_WRCLK_ROOT_SRC		335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IMX7D_WRCLK_ROOT_CG		336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IMX7D_WRCLK_ROOT_DIV		337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IMX7D_CLKO1_ROOT_SRC		338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IMX7D_CLKO1_ROOT_CG		339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IMX7D_CLKO1_ROOT_DIV		340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IMX7D_CLKO2_ROOT_SRC		341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IMX7D_CLKO2_ROOT_CG		342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IMX7D_CLKO2_ROOT_DIV		343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IMX7D_MAIN_AXI_ROOT_PRE_DIV	344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IMX7D_DISP_AXI_ROOT_PRE_DIV	345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IMX7D_ENET_AXI_ROOT_PRE_DIV	346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV	348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IMX7D_USB_HSIC_ROOT_PRE_DIV	349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IMX7D_PCIE_CTRL_ROOT_PRE_DIV	350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IMX7D_PCIE_PHY_ROOT_PRE_DIV	351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV	352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV	353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IMX7D_MIPI_DSI_ROOT_PRE_DIV	354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IMX7D_MIPI_CSI_ROOT_PRE_DIV	355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define IMX7D_MIPI_DPHY_ROOT_PRE_DIV	356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IMX7D_SAI1_ROOT_PRE_DIV		357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define IMX7D_SAI2_ROOT_PRE_DIV		358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define IMX7D_SAI3_ROOT_PRE_DIV		359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define IMX7D_SPDIF_ROOT_PRE_DIV	360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define IMX7D_ENET1_REF_ROOT_PRE_DIV	361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IMX7D_ENET1_TIME_ROOT_PRE_DIV	362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define IMX7D_ENET2_REF_ROOT_PRE_DIV	363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define IMX7D_ENET2_TIME_ROOT_PRE_DIV	364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define IMX7D_EIM_ROOT_PRE_DIV		366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define IMX7D_NAND_ROOT_PRE_DIV		367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IMX7D_QSPI_ROOT_PRE_DIV		368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define IMX7D_USDHC1_ROOT_PRE_DIV	369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define IMX7D_USDHC2_ROOT_PRE_DIV	370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define IMX7D_USDHC3_ROOT_PRE_DIV	371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define IMX7D_CAN1_ROOT_PRE_DIV		372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IMX7D_CAN2_ROOT_PRE_DIV		373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IMX7D_I2C1_ROOT_PRE_DIV		374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IMX7D_I2C2_ROOT_PRE_DIV		375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IMX7D_I2C3_ROOT_PRE_DIV		376
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define IMX7D_I2C4_ROOT_PRE_DIV		377
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define IMX7D_UART1_ROOT_PRE_DIV	378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IMX7D_UART2_ROOT_PRE_DIV	379
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define IMX7D_UART3_ROOT_PRE_DIV	380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IMX7D_UART4_ROOT_PRE_DIV	381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IMX7D_UART5_ROOT_PRE_DIV	382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IMX7D_UART6_ROOT_PRE_DIV	383
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IMX7D_UART7_ROOT_PRE_DIV	384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define IMX7D_ECSPI1_ROOT_PRE_DIV	385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define IMX7D_ECSPI2_ROOT_PRE_DIV	386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define IMX7D_ECSPI3_ROOT_PRE_DIV	387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IMX7D_ECSPI4_ROOT_PRE_DIV	388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IMX7D_PWM1_ROOT_PRE_DIV		389
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define IMX7D_PWM2_ROOT_PRE_DIV		390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define IMX7D_PWM3_ROOT_PRE_DIV		391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define IMX7D_PWM4_ROOT_PRE_DIV		392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define IMX7D_FLEXTIMER1_ROOT_PRE_DIV	393
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define IMX7D_FLEXTIMER2_ROOT_PRE_DIV	394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define IMX7D_SIM1_ROOT_PRE_DIV		395
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define IMX7D_SIM2_ROOT_PRE_DIV		396
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define IMX7D_GPT1_ROOT_PRE_DIV		397
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define IMX7D_GPT2_ROOT_PRE_DIV		398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define IMX7D_GPT3_ROOT_PRE_DIV		399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define IMX7D_GPT4_ROOT_PRE_DIV		400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define IMX7D_TRACE_ROOT_PRE_DIV	401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define IMX7D_WDOG_ROOT_PRE_DIV		402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define IMX7D_CSI_MCLK_ROOT_PRE_DIV	403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV	404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define IMX7D_WRCLK_ROOT_PRE_DIV	405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define IMX7D_CLKO1_ROOT_PRE_DIV	406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define IMX7D_CLKO2_ROOT_PRE_DIV	407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define IMX7D_DRAM_ALT_ROOT_PRE_DIV	409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define IMX7D_LVDS1_IN_CLK		410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define IMX7D_LVDS1_OUT_SEL		411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define IMX7D_LVDS1_OUT_CLK		412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define IMX7D_CLK_DUMMY			413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define IMX7D_GPT_3M_CLK		414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define IMX7D_OCRAM_CLK			415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define IMX7D_OCRAM_S_CLK		416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define IMX7D_WDOG2_ROOT_CLK		417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define IMX7D_WDOG3_ROOT_CLK		418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define IMX7D_WDOG4_ROOT_CLK		419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define IMX7D_SDMA_CORE_CLK		420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define IMX7D_USB1_MAIN_480M_CLK	421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define IMX7D_USB_CTRL_CLK		422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define IMX7D_USB_PHY1_CLK		423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define IMX7D_USB_PHY2_CLK		424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define IMX7D_IPG_ROOT_CLK		425
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define IMX7D_SAI1_IPG_CLK		426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define IMX7D_SAI2_IPG_CLK		427
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define IMX7D_SAI3_IPG_CLK		428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define IMX7D_PLL_AUDIO_TEST_DIV	429
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define IMX7D_PLL_AUDIO_POST_DIV	430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define IMX7D_PLL_VIDEO_TEST_DIV	431
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define IMX7D_PLL_VIDEO_POST_DIV	432
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define IMX7D_MU_ROOT_CLK		433
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define IMX7D_SEMA4_HS_ROOT_CLK		434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define IMX7D_PLL_DRAM_TEST_DIV		435
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define IMX7D_ADC_ROOT_CLK		436
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define IMX7D_CLK_ARM			437
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define IMX7D_CKIL			438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define IMX7D_OCOTP_CLK			439
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define IMX7D_NAND_RAWNAND_CLK		440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define IMX7D_SNVS_CLK			442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define IMX7D_CAAM_CLK			443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define IMX7D_KPP_ROOT_CLK		444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define IMX7D_PXP_CLK			445
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define IMX7D_CLK_END			446
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */