Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __DT_BINDINGS_CLOCK_IMX6UL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define IMX6UL_CLK_DUMMY		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define IMX6UL_CLK_CKIL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define IMX6UL_CLK_CKIH			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define IMX6UL_CLK_OSC			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define IMX6UL_PLL1_BYPASS_SRC		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define IMX6UL_PLL2_BYPASS_SRC		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define IMX6UL_PLL3_BYPASS_SRC		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IMX6UL_PLL4_BYPASS_SRC		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IMX6UL_PLL5_BYPASS_SRC		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IMX6UL_PLL6_BYPASS_SRC		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IMX6UL_PLL7_BYPASS_SRC		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IMX6UL_CLK_PLL1			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IMX6UL_CLK_PLL2			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IMX6UL_CLK_PLL3			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IMX6UL_CLK_PLL4			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IMX6UL_CLK_PLL5			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IMX6UL_CLK_PLL6			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IMX6UL_CLK_PLL7			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IMX6UL_PLL1_BYPASS		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IMX6UL_PLL2_BYPASS		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IMX6UL_PLL3_BYPASS		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IMX6UL_PLL4_BYPASS		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IMX6UL_PLL5_BYPASS		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IMX6UL_PLL6_BYPASS		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IMX6UL_PLL7_BYPASS		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IMX6UL_CLK_PLL1_SYS		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IMX6UL_CLK_PLL2_BUS		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IMX6UL_CLK_PLL3_USB_OTG		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IMX6UL_CLK_PLL4_AUDIO		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IMX6UL_CLK_PLL5_VIDEO		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IMX6UL_CLK_PLL6_ENET		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IMX6UL_CLK_PLL7_USB_HOST	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IMX6UL_CLK_USBPHY1		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IMX6UL_CLK_USBPHY2		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IMX6UL_CLK_USBPHY1_GATE		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IMX6UL_CLK_USBPHY2_GATE		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IMX6UL_CLK_PLL2_PFD0		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IMX6UL_CLK_PLL2_PFD1		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IMX6UL_CLK_PLL2_PFD2		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IMX6UL_CLK_PLL2_PFD3		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IMX6UL_CLK_PLL3_PFD0		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IMX6UL_CLK_PLL3_PFD1		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IMX6UL_CLK_PLL3_PFD2		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IMX6UL_CLK_PLL3_PFD3		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IMX6UL_CLK_ENET_REF		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IMX6UL_CLK_ENET2_REF		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IMX6UL_CLK_ENET2_REF_125M	46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IMX6UL_CLK_ENET_PTP_REF		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IMX6UL_CLK_ENET_PTP		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IMX6UL_CLK_PLL4_POST_DIV	49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IMX6UL_CLK_PLL4_AUDIO_DIV	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IMX6UL_CLK_PLL5_POST_DIV	51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IMX6UL_CLK_PLL5_VIDEO_DIV	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IMX6UL_CLK_PLL2_198M		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IMX6UL_CLK_PLL3_80M		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IMX6UL_CLK_PLL3_60M		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IMX6UL_CLK_STEP			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IMX6UL_CLK_PLL1_SW		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IMX6UL_CLK_AXI_ALT_SEL		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IMX6UL_CLK_AXI_SEL		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IMX6UL_CLK_PERIPH_PRE		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IMX6UL_CLK_PERIPH2_PRE		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IMX6UL_CLK_PERIPH_CLK2_SEL	62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IMX6UL_CLK_PERIPH2_CLK2_SEL	63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IMX6UL_CLK_USDHC1_SEL		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IMX6UL_CLK_USDHC2_SEL		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IMX6UL_CLK_BCH_SEL		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IMX6UL_CLK_GPMI_SEL		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IMX6UL_CLK_EIM_SLOW_SEL		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define IMX6UL_CLK_SPDIF_SEL		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IMX6UL_CLK_SAI1_SEL		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define IMX6UL_CLK_SAI2_SEL		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IMX6UL_CLK_SAI3_SEL		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define IMX6UL_CLK_LCDIF_PRE_SEL	73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IMX6UL_CLK_SIM_PRE_SEL		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IMX6UL_CLK_LDB_DI0_SEL		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IMX6UL_CLK_LDB_DI1_SEL		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IMX6UL_CLK_ENFC_SEL		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IMX6UL_CLK_CAN_SEL		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IMX6UL_CLK_ECSPI_SEL		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IMX6UL_CLK_UART_SEL		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IMX6UL_CLK_QSPI1_SEL		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define IMX6UL_CLK_PERCLK_SEL		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define IMX6UL_CLK_LCDIF_SEL		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define IMX6UL_CLK_SIM_SEL		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define IMX6UL_CLK_PERIPH		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define IMX6UL_CLK_PERIPH2		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IMX6UL_CLK_LDB_DI0_DIV_3_5	87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IMX6UL_CLK_LDB_DI0_DIV_7	88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IMX6UL_CLK_LDB_DI1_DIV_3_5	89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define IMX6UL_CLK_LDB_DI1_DIV_7	90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX6UL_CLK_LDB_DI0_DIV_SEL	91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX6UL_CLK_LDB_DI1_DIV_SEL	92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX6UL_CLK_ARM			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX6UL_CLK_PERIPH_CLK2		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX6UL_CLK_PERIPH2_CLK2		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX6UL_CLK_AHB			96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX6UL_CLK_MMDC_PODF		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX6UL_CLK_AXI_PODF		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX6UL_CLK_PERCLK		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX6UL_CLK_IPG			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX6UL_CLK_USDHC1_PODF		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX6UL_CLK_USDHC2_PODF		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX6UL_CLK_BCH_PODF		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX6UL_CLK_GPMI_PODF		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX6UL_CLK_EIM_SLOW_PODF	105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX6UL_CLK_SPDIF_PRED		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX6UL_CLK_SPDIF_PODF		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX6UL_CLK_SAI1_PRED		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX6UL_CLK_SAI1_PODF		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX6UL_CLK_SAI2_PRED		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX6UL_CLK_SAI2_PODF		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX6UL_CLK_SAI3_PRED		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX6UL_CLK_SAI3_PODF		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX6UL_CLK_LCDIF_PRED		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX6UL_CLK_LCDIF_PODF		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX6UL_CLK_SIM_PODF		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX6UL_CLK_QSPI1_PDOF		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX6UL_CLK_ENFC_PRED		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX6UL_CLK_ENFC_PODF		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX6UL_CLK_CAN_PODF		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX6UL_CLK_ECSPI_PODF		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX6UL_CLK_UART_PODF		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX6UL_CLK_ADC1			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX6UL_CLK_ADC2			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX6UL_CLK_AIPSTZ1		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX6UL_CLK_AIPSTZ2		126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX6UL_CLK_AIPSTZ3		127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX6UL_CLK_APBHDMA		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX6UL_CLK_ASRC_IPG		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX6UL_CLK_ASRC_MEM		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX6UL_CLK_GPMI_BCH_APB		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX6UL_CLK_GPMI_BCH		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX6UL_CLK_GPMI_IO		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX6UL_CLK_GPMI_APB		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX6UL_CLK_CAAM_MEM		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX6UL_CLK_CAAM_ACLK		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX6UL_CLK_CAAM_IPG		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX6UL_CLK_CSI			138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX6UL_CLK_ECSPI1		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX6UL_CLK_ECSPI2		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX6UL_CLK_ECSPI3		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX6UL_CLK_ECSPI4		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX6UL_CLK_EIM			143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX6UL_CLK_ENET			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX6UL_CLK_ENET_AHB		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX6UL_CLK_EPIT1		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX6UL_CLK_EPIT2		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX6UL_CLK_CAN1_IPG		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX6UL_CLK_CAN1_SERIAL		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX6UL_CLK_CAN2_IPG		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX6UL_CLK_CAN2_SERIAL		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX6UL_CLK_GPT1_BUS		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX6UL_CLK_GPT1_SERIAL		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX6UL_CLK_GPT2_BUS		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX6UL_CLK_GPT2_SERIAL		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX6UL_CLK_I2C1			156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX6UL_CLK_I2C2			157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX6UL_CLK_I2C3			158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX6UL_CLK_I2C4			159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX6UL_CLK_IOMUXC		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX6UL_CLK_LCDIF_APB		161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX6UL_CLK_LCDIF_PIX		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX6UL_CLK_MMDC_P0_FAST		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX6UL_CLK_MMDC_P0_IPG		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX6UL_CLK_OCOTP		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX6UL_CLK_OCRAM		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX6UL_CLK_PWM1			167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX6UL_CLK_PWM2			168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX6UL_CLK_PWM3			169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX6UL_CLK_PWM4			170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX6UL_CLK_PWM5			171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX6UL_CLK_PWM6			172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX6UL_CLK_PWM7			173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX6UL_CLK_PWM8			174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX6UL_CLK_PXP			175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX6UL_CLK_QSPI			176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX6UL_CLK_ROM			177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX6UL_CLK_SAI1			178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX6UL_CLK_SAI1_IPG		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX6UL_CLK_SAI2			180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX6UL_CLK_SAI2_IPG		181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX6UL_CLK_SAI3			182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX6UL_CLK_SAI3_IPG		183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX6UL_CLK_SDMA			184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX6UL_CLK_SIM			185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX6UL_CLK_SIM_S		186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX6UL_CLK_SPBA			187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX6UL_CLK_SPDIF		188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX6UL_CLK_UART1_IPG		189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX6UL_CLK_UART1_SERIAL		190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX6UL_CLK_UART2_IPG		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX6UL_CLK_UART2_SERIAL		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX6UL_CLK_UART3_IPG		193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX6UL_CLK_UART3_SERIAL		194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX6UL_CLK_UART4_IPG		195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX6UL_CLK_UART4_SERIAL		196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX6UL_CLK_UART5_IPG		197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX6UL_CLK_UART5_SERIAL		198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX6UL_CLK_UART6_IPG		199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX6UL_CLK_UART6_SERIAL		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX6UL_CLK_UART7_IPG		201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX6UL_CLK_UART7_SERIAL		202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX6UL_CLK_UART8_IPG		203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX6UL_CLK_UART8_SERIAL		204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX6UL_CLK_USBOH3		205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IMX6UL_CLK_USDHC1		206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX6UL_CLK_USDHC2		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMX6UL_CLK_WDOG1		208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX6UL_CLK_WDOG2		209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IMX6UL_CLK_WDOG3		210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX6UL_CLK_LDB_DI0		211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IMX6UL_CLK_AXI			212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX6UL_CLK_SPDIF_GCLK		213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IMX6UL_CLK_GPT_3M		214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX6UL_CLK_SIM2			215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMX6UL_CLK_SIM1			216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX6UL_CLK_IPP_DI0		217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IMX6UL_CLK_IPP_DI1		218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX6UL_CA7_SECONDARY_SEL	219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMX6UL_CLK_PER_BCH		220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX6UL_CLK_CSI_SEL		221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMX6UL_CLK_CSI_PODF		222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX6UL_CLK_PLL3_120M		223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMX6UL_CLK_KPP			224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX6ULL_CLK_ESAI_PRED		225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMX6ULL_CLK_ESAI_PODF		226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMX6ULL_CLK_ESAI_EXTAL		227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMX6ULL_CLK_ESAI_MEM		228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX6ULL_CLK_ESAI_IPG		229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IMX6ULL_CLK_DCP_CLK		230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX6ULL_CLK_EPDC_PRE_SEL	231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IMX6ULL_CLK_EPDC_SEL		232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX6ULL_CLK_EPDC_PODF		233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IMX6ULL_CLK_EPDC_ACLK		234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMX6ULL_CLK_EPDC_PIX		235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMX6ULL_CLK_ESAI_SEL		236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX6UL_CLK_CKO1_SEL		237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IMX6UL_CLK_CKO1_PODF		238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX6UL_CLK_CKO1			239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IMX6UL_CLK_CKO2_SEL		240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IMX6UL_CLK_CKO2_PODF		241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IMX6UL_CLK_CKO2			242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX6UL_CLK_CKO			243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMX6UL_CLK_GPIO1		244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX6UL_CLK_GPIO2		245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IMX6UL_CLK_GPIO3		246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX6UL_CLK_GPIO4		247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IMX6UL_CLK_GPIO5		248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX6UL_CLK_MMDC_P1_IPG		249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX6UL_CLK_END			250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */