Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __DT_BINDINGS_CLOCK_IMX6SX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define IMX6SX_CLK_DUMMY		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define IMX6SX_CLK_CKIL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define IMX6SX_CLK_CKIH			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define IMX6SX_CLK_OSC			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define IMX6SX_CLK_PLL1_SYS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define IMX6SX_CLK_PLL2_BUS		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define IMX6SX_CLK_PLL3_USB_OTG		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IMX6SX_CLK_PLL4_AUDIO		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IMX6SX_CLK_PLL5_VIDEO		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IMX6SX_CLK_PLL6_ENET		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IMX6SX_CLK_PLL7_USB_HOST	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IMX6SX_CLK_USBPHY1		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IMX6SX_CLK_USBPHY2		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IMX6SX_CLK_USBPHY1_GATE		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IMX6SX_CLK_USBPHY2_GATE		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IMX6SX_CLK_PCIE_REF		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IMX6SX_CLK_PCIE_REF_125M	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IMX6SX_CLK_ENET_REF		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IMX6SX_CLK_PLL2_PFD0		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IMX6SX_CLK_PLL2_PFD1		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IMX6SX_CLK_PLL2_PFD2		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IMX6SX_CLK_PLL2_PFD3		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IMX6SX_CLK_PLL3_PFD0		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IMX6SX_CLK_PLL3_PFD1		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IMX6SX_CLK_PLL3_PFD2		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IMX6SX_CLK_PLL3_PFD3		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IMX6SX_CLK_PLL2_198M		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IMX6SX_CLK_PLL3_120M		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IMX6SX_CLK_PLL3_80M		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IMX6SX_CLK_PLL3_60M		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IMX6SX_CLK_TWD			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IMX6SX_CLK_PLL4_POST_DIV	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IMX6SX_CLK_PLL4_AUDIO_DIV	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IMX6SX_CLK_PLL5_POST_DIV	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IMX6SX_CLK_PLL5_VIDEO_DIV	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IMX6SX_CLK_STEP			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IMX6SX_CLK_PLL1_SW		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IMX6SX_CLK_OCRAM_SEL		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IMX6SX_CLK_PERIPH_PRE		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IMX6SX_CLK_PERIPH2_PRE		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IMX6SX_CLK_PERIPH_CLK2_SEL	40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IMX6SX_CLK_PERIPH2_CLK2_SEL	41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IMX6SX_CLK_PCIE_AXI_SEL		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IMX6SX_CLK_GPU_AXI_SEL		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IMX6SX_CLK_GPU_CORE_SEL		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IMX6SX_CLK_EIM_SLOW_SEL		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IMX6SX_CLK_USDHC1_SEL		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IMX6SX_CLK_USDHC2_SEL		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IMX6SX_CLK_USDHC3_SEL		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IMX6SX_CLK_USDHC4_SEL		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IMX6SX_CLK_SSI1_SEL		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IMX6SX_CLK_SSI2_SEL		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IMX6SX_CLK_SSI3_SEL		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IMX6SX_CLK_QSPI1_SEL		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IMX6SX_CLK_PERCLK_SEL		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IMX6SX_CLK_VID_SEL		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IMX6SX_CLK_ESAI_SEL		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IMX6SX_CLK_LDB_DI0_DIV_SEL	57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IMX6SX_CLK_LDB_DI1_DIV_SEL	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IMX6SX_CLK_CAN_SEL		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IMX6SX_CLK_UART_SEL		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IMX6SX_CLK_QSPI2_SEL		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IMX6SX_CLK_LDB_DI1_SEL		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IMX6SX_CLK_LDB_DI0_SEL		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IMX6SX_CLK_SPDIF_SEL		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IMX6SX_CLK_AUDIO_SEL		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IMX6SX_CLK_ENET_PRE_SEL		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IMX6SX_CLK_ENET_SEL		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IMX6SX_CLK_M4_PRE_SEL		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define IMX6SX_CLK_M4_SEL		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IMX6SX_CLK_ECSPI_SEL		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define IMX6SX_CLK_LCDIF1_PRE_SEL	71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IMX6SX_CLK_LCDIF2_PRE_SEL	72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define IMX6SX_CLK_LCDIF1_SEL		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IMX6SX_CLK_LCDIF2_SEL		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IMX6SX_CLK_DISPLAY_SEL		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IMX6SX_CLK_CSI_SEL		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IMX6SX_CLK_CKO1_SEL		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IMX6SX_CLK_CKO2_SEL		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IMX6SX_CLK_CKO			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IMX6SX_CLK_PERIPH_CLK2		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IMX6SX_CLK_PERIPH2_CLK2		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define IMX6SX_CLK_IPG			82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define IMX6SX_CLK_GPU_CORE_PODF	83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define IMX6SX_CLK_GPU_AXI_PODF		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define IMX6SX_CLK_LCDIF1_PODF		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define IMX6SX_CLK_QSPI1_PODF		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IMX6SX_CLK_EIM_SLOW_PODF	87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IMX6SX_CLK_LCDIF2_PODF		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IMX6SX_CLK_PERCLK		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define IMX6SX_CLK_VID_PODF		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX6SX_CLK_CAN_PODF		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX6SX_CLK_USDHC1_PODF		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX6SX_CLK_USDHC2_PODF		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX6SX_CLK_USDHC3_PODF		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX6SX_CLK_USDHC4_PODF		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX6SX_CLK_UART_PODF		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX6SX_CLK_ESAI_PRED		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX6SX_CLK_ESAI_PODF		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX6SX_CLK_SSI3_PRED		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX6SX_CLK_SSI3_PODF		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX6SX_CLK_SSI1_PRED		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX6SX_CLK_SSI1_PODF		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX6SX_CLK_QSPI2_PRED		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX6SX_CLK_QSPI2_PODF		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX6SX_CLK_SSI2_PRED		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX6SX_CLK_SSI2_PODF		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX6SX_CLK_SPDIF_PRED		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX6SX_CLK_SPDIF_PODF		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX6SX_CLK_AUDIO_PRED		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX6SX_CLK_AUDIO_PODF		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX6SX_CLK_ENET_PODF		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX6SX_CLK_M4_PODF		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX6SX_CLK_ECSPI_PODF		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX6SX_CLK_LCDIF1_PRED		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX6SX_CLK_LCDIF2_PRED		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX6SX_CLK_DISPLAY_PODF		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX6SX_CLK_CSI_PODF		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX6SX_CLK_LDB_DI0_DIV_3_5	118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX6SX_CLK_LDB_DI0_DIV_7	119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX6SX_CLK_LDB_DI1_DIV_3_5	120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX6SX_CLK_LDB_DI1_DIV_7	121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX6SX_CLK_CKO1_PODF		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX6SX_CLK_CKO2_PODF		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX6SX_CLK_PERIPH		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX6SX_CLK_PERIPH2		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX6SX_CLK_OCRAM		126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX6SX_CLK_AHB			127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX6SX_CLK_MMDC_PODF		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX6SX_CLK_ARM			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX6SX_CLK_AIPS_TZ1		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX6SX_CLK_AIPS_TZ2		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX6SX_CLK_APBH_DMA		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX6SX_CLK_ASRC_GATE		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX6SX_CLK_CAAM_MEM		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX6SX_CLK_CAAM_ACLK		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX6SX_CLK_CAAM_IPG		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX6SX_CLK_CAN1_IPG		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX6SX_CLK_CAN1_SERIAL		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX6SX_CLK_CAN2_IPG		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX6SX_CLK_CAN2_SERIAL		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX6SX_CLK_CPU_DEBUG		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX6SX_CLK_DCIC1		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX6SX_CLK_DCIC2		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX6SX_CLK_AIPS_TZ3		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX6SX_CLK_ECSPI1		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX6SX_CLK_ECSPI2		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX6SX_CLK_ECSPI3		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX6SX_CLK_ECSPI4		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX6SX_CLK_ECSPI5		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX6SX_CLK_EPIT1		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX6SX_CLK_EPIT2		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX6SX_CLK_ESAI_EXTAL		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX6SX_CLK_WAKEUP		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX6SX_CLK_GPT_BUS		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX6SX_CLK_GPT_SERIAL		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX6SX_CLK_GPU			156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX6SX_CLK_OCRAM_S		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX6SX_CLK_CANFD		158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX6SX_CLK_CSI			159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX6SX_CLK_I2C1			160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX6SX_CLK_I2C2			161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX6SX_CLK_I2C3			162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX6SX_CLK_OCOTP		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX6SX_CLK_IOMUXC		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX6SX_CLK_IPMUX1		165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX6SX_CLK_IPMUX2		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX6SX_CLK_IPMUX3		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX6SX_CLK_TZASC1		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX6SX_CLK_LCDIF_APB		169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX6SX_CLK_PXP_AXI		170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX6SX_CLK_M4			171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX6SX_CLK_ENET			172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX6SX_CLK_DISPLAY_AXI		173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX6SX_CLK_LCDIF2_PIX		174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX6SX_CLK_LCDIF1_PIX		175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX6SX_CLK_LDB_DI0		176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX6SX_CLK_QSPI1		177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX6SX_CLK_MLB			178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX6SX_CLK_MMDC_P0_FAST		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX6SX_CLK_MMDC_P0_IPG		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX6SX_CLK_AXI			181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX6SX_CLK_PCIE_AXI		182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX6SX_CLK_QSPI2		183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX6SX_CLK_PER1_BCH		184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX6SX_CLK_PER2_MAIN		185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX6SX_CLK_PWM1			186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX6SX_CLK_PWM2			187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX6SX_CLK_PWM3			188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX6SX_CLK_PWM4			189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX6SX_CLK_GPMI_BCH_APB		190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX6SX_CLK_GPMI_BCH		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX6SX_CLK_GPMI_IO		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX6SX_CLK_GPMI_APB		193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX6SX_CLK_ROM			194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX6SX_CLK_SDMA			195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX6SX_CLK_SPBA			196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX6SX_CLK_SPDIF		197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX6SX_CLK_SSI1_IPG		198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX6SX_CLK_SSI2_IPG		199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX6SX_CLK_SSI3_IPG		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX6SX_CLK_SSI1			201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX6SX_CLK_SSI2			202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX6SX_CLK_SSI3			203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX6SX_CLK_UART_IPG		204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX6SX_CLK_UART_SERIAL		205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IMX6SX_CLK_SAI1			206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX6SX_CLK_SAI2			207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMX6SX_CLK_USBOH3		208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX6SX_CLK_USDHC1		209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IMX6SX_CLK_USDHC2		210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX6SX_CLK_USDHC3		211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IMX6SX_CLK_USDHC4		212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX6SX_CLK_EIM_SLOW		213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IMX6SX_CLK_PWM8			214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX6SX_CLK_VADC			215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMX6SX_CLK_GIS			216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX6SX_CLK_I2C4			217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IMX6SX_CLK_PWM5			218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX6SX_CLK_PWM6			219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMX6SX_CLK_PWM7			220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX6SX_CLK_CKO1			221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMX6SX_CLK_CKO2			222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX6SX_CLK_IPP_DI0		223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMX6SX_CLK_IPP_DI1		224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX6SX_CLK_ENET_AHB		225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMX6SX_CLK_OCRAM_PODF		226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMX6SX_CLK_GPT_3M		227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMX6SX_CLK_ENET_PTP		228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX6SX_CLK_ENET_PTP_REF		229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IMX6SX_CLK_ENET2_REF		230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX6SX_CLK_ENET2_REF_125M	231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IMX6SX_CLK_AUDIO		232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX6SX_CLK_LVDS1_SEL		233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IMX6SX_CLK_LVDS1_OUT		234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMX6SX_CLK_ASRC_IPG		235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMX6SX_CLK_ASRC_MEM		236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX6SX_CLK_SAI1_IPG		237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IMX6SX_CLK_SAI2_IPG		238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX6SX_CLK_ESAI_IPG		239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IMX6SX_CLK_ESAI_MEM		240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IMX6SX_CLK_LVDS1_IN		241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IMX6SX_CLK_ANACLK1		242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX6SX_PLL1_BYPASS_SRC		243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMX6SX_PLL2_BYPASS_SRC		244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX6SX_PLL3_BYPASS_SRC		245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IMX6SX_PLL4_BYPASS_SRC		246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX6SX_PLL5_BYPASS_SRC		247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IMX6SX_PLL6_BYPASS_SRC		248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX6SX_PLL7_BYPASS_SRC		249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IMX6SX_CLK_PLL1			250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX6SX_CLK_PLL2			251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IMX6SX_CLK_PLL3			252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IMX6SX_CLK_PLL4			253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IMX6SX_CLK_PLL5			254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IMX6SX_CLK_PLL6			255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IMX6SX_CLK_PLL7			256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMX6SX_PLL1_BYPASS		257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IMX6SX_PLL2_BYPASS		258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX6SX_PLL3_BYPASS		259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMX6SX_PLL4_BYPASS		260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX6SX_PLL5_BYPASS		261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMX6SX_PLL6_BYPASS		262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IMX6SX_PLL7_BYPASS		263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IMX6SX_CLK_SPDIF_GCLK		264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IMX6SX_CLK_LVDS2_SEL		265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IMX6SX_CLK_LVDS2_OUT		266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IMX6SX_CLK_LVDS2_IN		267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IMX6SX_CLK_ANACLK2		268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IMX6SX_CLK_MMDC_P1_IPG		269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IMX6SX_CLK_CLK_END		270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */