^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017-2018 NXP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DT_BINDINGS_CLOCK_IMX6SLL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX6SLL_CLK_DUMMY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX6SLL_CLK_CKIL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX6SLL_CLK_OSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX6SLL_PLL1_BYPASS_SRC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX6SLL_PLL2_BYPASS_SRC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX6SLL_PLL3_BYPASS_SRC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX6SLL_PLL4_BYPASS_SRC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX6SLL_PLL5_BYPASS_SRC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX6SLL_PLL6_BYPASS_SRC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX6SLL_PLL7_BYPASS_SRC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX6SLL_CLK_PLL1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX6SLL_CLK_PLL2 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX6SLL_CLK_PLL3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX6SLL_CLK_PLL4 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX6SLL_CLK_PLL5 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX6SLL_CLK_PLL6 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX6SLL_CLK_PLL7 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX6SLL_PLL1_BYPASS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX6SLL_PLL2_BYPASS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX6SLL_PLL3_BYPASS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX6SLL_PLL4_BYPASS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX6SLL_PLL5_BYPASS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX6SLL_PLL6_BYPASS 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX6SLL_PLL7_BYPASS 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX6SLL_CLK_PLL1_SYS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX6SLL_CLK_PLL2_BUS 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX6SLL_CLK_PLL3_USB_OTG 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX6SLL_CLK_PLL4_AUDIO 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX6SLL_CLK_PLL5_VIDEO 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX6SLL_CLK_PLL6_ENET 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX6SLL_CLK_PLL7_USB_HOST 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX6SLL_CLK_USBPHY1 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX6SLL_CLK_USBPHY2 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX6SLL_CLK_USBPHY1_GATE 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX6SLL_CLK_USBPHY2_GATE 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX6SLL_CLK_PLL2_PFD0 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX6SLL_CLK_PLL2_PFD1 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX6SLL_CLK_PLL2_PFD2 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX6SLL_CLK_PLL2_PFD3 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX6SLL_CLK_PLL3_PFD0 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX6SLL_CLK_PLL3_PFD1 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX6SLL_CLK_PLL3_PFD2 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX6SLL_CLK_PLL3_PFD3 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX6SLL_CLK_PLL4_POST_DIV 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX6SLL_CLK_PLL4_AUDIO_DIV 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX6SLL_CLK_PLL5_POST_DIV 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX6SLL_CLK_PLL5_VIDEO_DIV 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX6SLL_CLK_PLL2_198M 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX6SLL_CLK_PLL3_120M 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX6SLL_CLK_PLL3_80M 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX6SLL_CLK_PLL3_60M 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX6SLL_CLK_STEP 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX6SLL_CLK_PLL1_SW 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX6SLL_CLK_AXI_ALT_SEL 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX6SLL_CLK_AXI_SEL 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX6SLL_CLK_PERIPH_PRE 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX6SLL_CLK_PERIPH2_PRE 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX6SLL_CLK_PERIPH_CLK2_SEL 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX6SLL_CLK_PERCLK_SEL 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX6SLL_CLK_USDHC1_SEL 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX6SLL_CLK_USDHC2_SEL 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX6SLL_CLK_USDHC3_SEL 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX6SLL_CLK_SSI1_SEL 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX6SLL_CLK_SSI2_SEL 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX6SLL_CLK_SSI3_SEL 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX6SLL_CLK_PXP_SEL 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX6SLL_CLK_LCDIF_PRE_SEL 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX6SLL_CLK_LCDIF_SEL 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX6SLL_CLK_EPDC_PRE_SEL 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX6SLL_CLK_SPDIF_SEL 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX6SLL_CLK_ECSPI_SEL 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX6SLL_CLK_UART_SEL 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX6SLL_CLK_ARM 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX6SLL_CLK_PERIPH 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX6SLL_CLK_PERIPH2 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX6SLL_CLK_PERIPH2_CLK2 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX6SLL_CLK_PERIPH_CLK2 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX6SLL_CLK_MMDC_PODF 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX6SLL_CLK_AXI_PODF 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX6SLL_CLK_AHB 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX6SLL_CLK_IPG 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX6SLL_CLK_PERCLK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX6SLL_CLK_USDHC1_PODF 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX6SLL_CLK_USDHC2_PODF 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX6SLL_CLK_USDHC3_PODF 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX6SLL_CLK_SSI1_PRED 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX6SLL_CLK_SSI2_PRED 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX6SLL_CLK_SSI3_PRED 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX6SLL_CLK_SSI1_PODF 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX6SLL_CLK_SSI2_PODF 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX6SLL_CLK_SSI3_PODF 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX6SLL_CLK_PXP_PODF 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX6SLL_CLK_LCDIF_PRED 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX6SLL_CLK_LCDIF_PODF 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX6SLL_CLK_EPDC_SEL 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX6SLL_CLK_EPDC_PODF 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX6SLL_CLK_SPDIF_PRED 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX6SLL_CLK_SPDIF_PODF 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX6SLL_CLK_ECSPI_PODF 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX6SLL_CLK_UART_PODF 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* CCGR 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX6SLL_CLK_AIPSTZ1 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX6SLL_CLK_AIPSTZ2 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX6SLL_CLK_DCP 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX6SLL_CLK_UART2_IPG 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX6SLL_CLK_UART2_SERIAL 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* CCGR 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX6SLL_CLK_ECSPI1 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX6SLL_CLK_ECSPI2 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX6SLL_CLK_ECSPI3 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX6SLL_CLK_ECSPI4 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX6SLL_CLK_UART3_IPG 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX6SLL_CLK_UART3_SERIAL 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX6SLL_CLK_UART4_IPG 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX6SLL_CLK_UART4_SERIAL 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX6SLL_CLK_EPIT1 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX6SLL_CLK_EPIT2 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX6SLL_CLK_GPT_BUS 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX6SLL_CLK_GPT_SERIAL 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* CCGR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX6SLL_CLK_CSI 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX6SLL_CLK_I2C1 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX6SLL_CLK_I2C2 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX6SLL_CLK_I2C3 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX6SLL_CLK_OCOTP 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX6SLL_CLK_LCDIF_APB 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX6SLL_CLK_PXP 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* CCGR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX6SLL_CLK_UART5_IPG 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX6SLL_CLK_UART5_SERIAL 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX6SLL_CLK_EPDC_AXI 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX6SLL_CLK_EPDC_PIX 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX6SLL_CLK_LCDIF_PIX 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX6SLL_CLK_WDOG1 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX6SLL_CLK_MMDC_P0_FAST 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX6SLL_CLK_MMDC_P0_IPG 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX6SLL_CLK_OCRAM 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* CCGR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX6SLL_CLK_PWM1 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX6SLL_CLK_PWM2 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX6SLL_CLK_PWM3 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX6SLL_CLK_PWM4 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* CCGR 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX6SLL_CLK_ROM 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX6SLL_CLK_SDMA 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX6SLL_CLK_KPP 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX6SLL_CLK_WDOG2 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX6SLL_CLK_SPBA 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX6SLL_CLK_SPDIF 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX6SLL_CLK_SPDIF_GCLK 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX6SLL_CLK_SSI1 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX6SLL_CLK_SSI1_IPG 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX6SLL_CLK_SSI2 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX6SLL_CLK_SSI2_IPG 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX6SLL_CLK_SSI3 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX6SLL_CLK_SSI3_IPG 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX6SLL_CLK_UART1_IPG 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX6SLL_CLK_UART1_SERIAL 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* CCGR 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX6SLL_CLK_USBOH3 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX6SLL_CLK_USDHC1 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX6SLL_CLK_USDHC2 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX6SLL_CLK_USDHC3 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX6SLL_CLK_IPP_DI0 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX6SLL_CLK_IPP_DI1 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX6SLL_CLK_LDB_DI0_SEL 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX6SLL_CLK_LDB_DI0_DIV_7 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX6SLL_CLK_LDB_DI0 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX6SLL_CLK_LDB_DI1_SEL 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX6SLL_CLK_LDB_DI1_DIV_7 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX6SLL_CLK_LDB_DI1 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX6SLL_CLK_EXTERN_AUDIO 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX6SLL_CLK_GPIO1 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX6SLL_CLK_GPIO2 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX6SLL_CLK_GPIO3 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX6SLL_CLK_GPIO4 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX6SLL_CLK_GPIO5 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX6SLL_CLK_GPIO6 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX6SLL_CLK_MMDC_P1_IPG 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX6SLL_CLK_END 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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