^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DT_BINDINGS_CLOCK_IMX6SL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define IMX6SL_CLK_DUMMY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IMX6SL_CLK_CKIL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX6SL_CLK_OSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX6SL_CLK_PLL1_SYS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX6SL_CLK_PLL2_BUS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX6SL_CLK_PLL3_USB_OTG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX6SL_CLK_PLL4_AUDIO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX6SL_CLK_PLL5_VIDEO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX6SL_CLK_PLL6_ENET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX6SL_CLK_PLL7_USB_HOST 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX6SL_CLK_USBPHY1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX6SL_CLK_USBPHY2 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX6SL_CLK_USBPHY1_GATE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX6SL_CLK_USBPHY2_GATE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX6SL_CLK_PLL4_POST_DIV 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX6SL_CLK_PLL5_POST_DIV 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX6SL_CLK_PLL5_VIDEO_DIV 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX6SL_CLK_ENET_REF 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX6SL_CLK_PLL2_PFD0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX6SL_CLK_PLL2_PFD1 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX6SL_CLK_PLL2_PFD2 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX6SL_CLK_PLL3_PFD0 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX6SL_CLK_PLL3_PFD1 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX6SL_CLK_PLL3_PFD2 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX6SL_CLK_PLL3_PFD3 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX6SL_CLK_PLL2_198M 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX6SL_CLK_PLL3_120M 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX6SL_CLK_PLL3_80M 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX6SL_CLK_PLL3_60M 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX6SL_CLK_STEP 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX6SL_CLK_PLL1_SW 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX6SL_CLK_OCRAM_ALT_SEL 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX6SL_CLK_OCRAM_SEL 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX6SL_CLK_PRE_PERIPH2_SEL 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX6SL_CLK_PRE_PERIPH_SEL 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX6SL_CLK_PERIPH_CLK2_SEL 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX6SL_CLK_CSI_SEL 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX6SL_CLK_LCDIF_AXI_SEL 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX6SL_CLK_USDHC1_SEL 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX6SL_CLK_USDHC2_SEL 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX6SL_CLK_USDHC3_SEL 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX6SL_CLK_USDHC4_SEL 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX6SL_CLK_SSI1_SEL 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX6SL_CLK_SSI2_SEL 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX6SL_CLK_SSI3_SEL 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX6SL_CLK_PERCLK_SEL 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX6SL_CLK_PXP_AXI_SEL 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX6SL_CLK_EPDC_AXI_SEL 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX6SL_CLK_GPU2D_OVG_SEL 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX6SL_CLK_GPU2D_SEL 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX6SL_CLK_LCDIF_PIX_SEL 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX6SL_CLK_EPDC_PIX_SEL 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX6SL_CLK_SPDIF0_SEL 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX6SL_CLK_SPDIF1_SEL 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX6SL_CLK_ECSPI_SEL 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX6SL_CLK_UART_SEL 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX6SL_CLK_PERIPH 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX6SL_CLK_PERIPH2 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX6SL_CLK_OCRAM_PODF 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX6SL_CLK_PERIPH_CLK2_PODF 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX6SL_CLK_PERIPH2_CLK2_PODF 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX6SL_CLK_IPG 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX6SL_CLK_CSI_PODF 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX6SL_CLK_LCDIF_AXI_PODF 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX6SL_CLK_USDHC1_PODF 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX6SL_CLK_USDHC2_PODF 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX6SL_CLK_USDHC3_PODF 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX6SL_CLK_USDHC4_PODF 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX6SL_CLK_SSI1_PRED 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX6SL_CLK_SSI1_PODF 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX6SL_CLK_SSI2_PRED 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX6SL_CLK_SSI2_PODF 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX6SL_CLK_SSI3_PRED 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX6SL_CLK_SSI3_PODF 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX6SL_CLK_PERCLK 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX6SL_CLK_PXP_AXI_PODF 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX6SL_CLK_EPDC_AXI_PODF 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX6SL_CLK_GPU2D_OVG_PODF 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX6SL_CLK_GPU2D_PODF 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX6SL_CLK_LCDIF_PIX_PRED 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX6SL_CLK_EPDC_PIX_PRED 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX6SL_CLK_LCDIF_PIX_PODF 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX6SL_CLK_EPDC_PIX_PODF 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX6SL_CLK_SPDIF0_PRED 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX6SL_CLK_SPDIF0_PODF 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX6SL_CLK_SPDIF1_PRED 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX6SL_CLK_SPDIF1_PODF 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX6SL_CLK_ECSPI_ROOT 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX6SL_CLK_UART_ROOT 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX6SL_CLK_AHB 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX6SL_CLK_MMDC_ROOT 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX6SL_CLK_ARM 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX6SL_CLK_ECSPI1 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX6SL_CLK_ECSPI2 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX6SL_CLK_ECSPI3 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX6SL_CLK_ECSPI4 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX6SL_CLK_EPIT1 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX6SL_CLK_EPIT2 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX6SL_CLK_EXTERN_AUDIO 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX6SL_CLK_GPT 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX6SL_CLK_GPT_SERIAL 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX6SL_CLK_GPU2D_OVG 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX6SL_CLK_I2C1 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX6SL_CLK_I2C2 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX6SL_CLK_I2C3 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX6SL_CLK_OCOTP 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX6SL_CLK_CSI 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX6SL_CLK_PXP_AXI 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX6SL_CLK_EPDC_AXI 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX6SL_CLK_LCDIF_AXI 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX6SL_CLK_LCDIF_PIX 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX6SL_CLK_EPDC_PIX 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX6SL_CLK_OCRAM 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX6SL_CLK_PWM1 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX6SL_CLK_PWM2 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX6SL_CLK_PWM3 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX6SL_CLK_PWM4 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX6SL_CLK_SDMA 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX6SL_CLK_SPDIF 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX6SL_CLK_SSI1 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX6SL_CLK_SSI2 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX6SL_CLK_SSI3 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX6SL_CLK_UART 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX6SL_CLK_UART_SERIAL 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX6SL_CLK_USBOH3 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX6SL_CLK_USDHC1 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX6SL_CLK_USDHC2 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX6SL_CLK_USDHC3 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX6SL_CLK_USDHC4 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX6SL_CLK_PLL4_AUDIO_DIV 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX6SL_CLK_SPBA 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX6SL_CLK_ENET 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX6SL_CLK_LVDS1_SEL 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX6SL_CLK_LVDS1_OUT 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX6SL_CLK_LVDS1_IN 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX6SL_CLK_ANACLK1 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX6SL_PLL1_BYPASS_SRC 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX6SL_PLL2_BYPASS_SRC 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX6SL_PLL3_BYPASS_SRC 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX6SL_PLL4_BYPASS_SRC 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX6SL_PLL5_BYPASS_SRC 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX6SL_PLL6_BYPASS_SRC 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX6SL_PLL7_BYPASS_SRC 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX6SL_CLK_PLL1 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX6SL_CLK_PLL2 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX6SL_CLK_PLL3 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX6SL_CLK_PLL4 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX6SL_CLK_PLL5 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX6SL_CLK_PLL6 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX6SL_CLK_PLL7 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX6SL_PLL1_BYPASS 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX6SL_PLL2_BYPASS 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX6SL_PLL3_BYPASS 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX6SL_PLL4_BYPASS 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX6SL_PLL5_BYPASS 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX6SL_PLL6_BYPASS 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX6SL_PLL7_BYPASS 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX6SL_CLK_SSI1_IPG 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX6SL_CLK_SSI2_IPG 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX6SL_CLK_SSI3_IPG 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX6SL_CLK_SPDIF_GCLK 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX6SL_CLK_MMDC_P0_IPG 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX6SL_CLK_MMDC_P1_IPG 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX6SL_CLK_END 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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