Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __DT_BINDINGS_CLOCK_IMX6QDL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define IMX6QDL_CLK_DUMMY			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define IMX6QDL_CLK_CKIL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define IMX6QDL_CLK_CKIH			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define IMX6QDL_CLK_OSC				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define IMX6QDL_CLK_PLL2_PFD0_352M		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define IMX6QDL_CLK_PLL2_PFD1_594M		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define IMX6QDL_CLK_PLL2_PFD2_396M		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IMX6QDL_CLK_PLL3_PFD0_720M		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IMX6QDL_CLK_PLL3_PFD1_540M		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IMX6QDL_CLK_PLL3_PFD2_508M		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IMX6QDL_CLK_PLL3_PFD3_454M		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IMX6QDL_CLK_PLL2_198M			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IMX6QDL_CLK_PLL3_120M			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IMX6QDL_CLK_PLL3_80M			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IMX6QDL_CLK_PLL3_60M			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IMX6QDL_CLK_TWD				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IMX6QDL_CLK_STEP			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IMX6QDL_CLK_PLL1_SW			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IMX6QDL_CLK_PERIPH_PRE			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IMX6QDL_CLK_PERIPH2_PRE			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IMX6QDL_CLK_PERIPH_CLK2_SEL		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IMX6QDL_CLK_PERIPH2_CLK2_SEL		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IMX6QDL_CLK_AXI_SEL			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IMX6QDL_CLK_ESAI_SEL			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IMX6QDL_CLK_ASRC_SEL			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IMX6QDL_CLK_SPDIF_SEL			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IMX6QDL_CLK_GPU2D_AXI			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IMX6QDL_CLK_GPU3D_AXI			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define IMX6QDL_CLK_GPU2D_CORE_SEL		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define IMX6QDL_CLK_GPU3D_CORE_SEL		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IMX6QDL_CLK_GPU3D_SHADER_SEL		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IMX6QDL_CLK_IPU1_SEL			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IMX6QDL_CLK_IPU2_SEL			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IMX6QDL_CLK_LDB_DI0_SEL			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IMX6QDL_CLK_LDB_DI1_SEL			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IMX6QDL_CLK_IPU1_DI0_PRE_SEL		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IMX6QDL_CLK_IPU1_DI1_PRE_SEL		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IMX6QDL_CLK_IPU2_DI0_PRE_SEL		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IMX6QDL_CLK_IPU2_DI1_PRE_SEL		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IMX6QDL_CLK_IPU1_DI0_SEL		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IMX6QDL_CLK_IPU1_DI1_SEL		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IMX6QDL_CLK_IPU2_DI0_SEL		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IMX6QDL_CLK_IPU2_DI1_SEL		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IMX6QDL_CLK_HSI_TX_SEL			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IMX6QDL_CLK_PCIE_AXI_SEL		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IMX6QDL_CLK_SSI1_SEL			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IMX6QDL_CLK_SSI2_SEL			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IMX6QDL_CLK_SSI3_SEL			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IMX6QDL_CLK_USDHC1_SEL			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define IMX6QDL_CLK_USDHC2_SEL			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IMX6QDL_CLK_USDHC3_SEL			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IMX6QDL_CLK_USDHC4_SEL			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IMX6QDL_CLK_ENFC_SEL			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IMX6QDL_CLK_EIM_SEL			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IMX6QDL_CLK_EIM_SLOW_SEL		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IMX6QDL_CLK_VDO_AXI_SEL			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IMX6QDL_CLK_VPU_AXI_SEL			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define IMX6QDL_CLK_CKO1_SEL			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IMX6QDL_CLK_PERIPH			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IMX6QDL_CLK_PERIPH2			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IMX6QDL_CLK_PERIPH_CLK2			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IMX6QDL_CLK_PERIPH2_CLK2		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IMX6QDL_CLK_IPG				62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define IMX6QDL_CLK_IPG_PER			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define IMX6QDL_CLK_ESAI_PRED			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define IMX6QDL_CLK_ESAI_PODF			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IMX6QDL_CLK_ASRC_PRED			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IMX6QDL_CLK_ASRC_PODF			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IMX6QDL_CLK_SPDIF_PRED			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define IMX6QDL_CLK_SPDIF_PODF			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IMX6QDL_CLK_CAN_ROOT			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define IMX6QDL_CLK_ECSPI_ROOT			71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IMX6QDL_CLK_GPU2D_CORE_PODF		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define IMX6QDL_CLK_GPU3D_CORE_PODF		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IMX6QDL_CLK_GPU3D_SHADER		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IMX6QDL_CLK_IPU1_PODF			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IMX6QDL_CLK_IPU2_PODF			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IMX6QDL_CLK_LDB_DI0_PODF		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IMX6QDL_CLK_LDB_DI1_PODF		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IMX6QDL_CLK_IPU1_DI0_PRE		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IMX6QDL_CLK_IPU1_DI1_PRE		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IMX6QDL_CLK_IPU2_DI0_PRE		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define IMX6QDL_CLK_IPU2_DI1_PRE		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define IMX6QDL_CLK_HSI_TX_PODF			83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define IMX6QDL_CLK_SSI1_PRED			84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define IMX6QDL_CLK_SSI1_PODF			85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define IMX6QDL_CLK_SSI2_PRED			86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IMX6QDL_CLK_SSI2_PODF			87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IMX6QDL_CLK_SSI3_PRED			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IMX6QDL_CLK_SSI3_PODF			89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define IMX6QDL_CLK_UART_SERIAL_PODF		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX6QDL_CLK_USDHC1_PODF			91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX6QDL_CLK_USDHC2_PODF			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX6QDL_CLK_USDHC3_PODF			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX6QDL_CLK_USDHC4_PODF			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX6QDL_CLK_ENFC_PRED			95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX6QDL_CLK_ENFC_PODF			96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX6QDL_CLK_EIM_PODF			97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX6QDL_CLK_EIM_SLOW_PODF		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX6QDL_CLK_VPU_AXI_PODF		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX6QDL_CLK_CKO1_PODF			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX6QDL_CLK_AXI				101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX6QDL_CLK_MMDC_CH0_AXI_PODF		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX6QDL_CLK_MMDC_CH1_AXI_PODF		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX6QDL_CLK_ARM				104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX6QDL_CLK_AHB				105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX6QDL_CLK_APBH_DMA			106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX6QDL_CLK_ASRC			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX6QDL_CLK_CAN1_IPG			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX6QDL_CLK_CAN1_SERIAL			109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX6QDL_CLK_CAN2_IPG			110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX6QDL_CLK_CAN2_SERIAL			111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX6QDL_CLK_ECSPI1			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX6QDL_CLK_ECSPI2			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX6QDL_CLK_ECSPI3			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX6QDL_CLK_ECSPI4			115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX6Q_CLK_ECSPI5			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX6DL_CLK_I2C4				116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX6QDL_CLK_ENET			117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX6QDL_CLK_ESAI_EXTAL			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX6QDL_CLK_GPT_IPG			119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX6QDL_CLK_GPT_IPG_PER			120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX6QDL_CLK_GPU2D_CORE			121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX6QDL_CLK_GPU3D_CORE			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX6QDL_CLK_HDMI_IAHB			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX6QDL_CLK_HDMI_ISFR			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX6QDL_CLK_I2C1			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX6QDL_CLK_I2C2			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX6QDL_CLK_I2C3			127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX6QDL_CLK_IIM				128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX6QDL_CLK_ENFC			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX6QDL_CLK_IPU1			130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX6QDL_CLK_IPU1_DI0			131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX6QDL_CLK_IPU1_DI1			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX6QDL_CLK_IPU2			133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX6QDL_CLK_IPU2_DI0			134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX6QDL_CLK_LDB_DI0			135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX6QDL_CLK_LDB_DI1			136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX6QDL_CLK_IPU2_DI1			137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX6QDL_CLK_HSI_TX			138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX6QDL_CLK_MLB				139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX6QDL_CLK_MMDC_CH0_AXI		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX6QDL_CLK_MMDC_CH1_AXI		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX6QDL_CLK_OCRAM			142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX6QDL_CLK_OPENVG_AXI			143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX6QDL_CLK_PCIE_AXI			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX6QDL_CLK_PWM1			145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX6QDL_CLK_PWM2			146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX6QDL_CLK_PWM3			147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX6QDL_CLK_PWM4			148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX6QDL_CLK_PER1_BCH			149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX6QDL_CLK_GPMI_BCH_APB		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX6QDL_CLK_GPMI_BCH			151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX6QDL_CLK_GPMI_IO			152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX6QDL_CLK_GPMI_APB			153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX6QDL_CLK_SATA			154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX6QDL_CLK_SDMA			155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX6QDL_CLK_SPBA			156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX6QDL_CLK_SSI1			157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX6QDL_CLK_SSI2			158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX6QDL_CLK_SSI3			159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX6QDL_CLK_UART_IPG			160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX6QDL_CLK_UART_SERIAL			161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX6QDL_CLK_USBOH3			162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX6QDL_CLK_USDHC1			163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX6QDL_CLK_USDHC2			164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX6QDL_CLK_USDHC3			165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX6QDL_CLK_USDHC4			166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX6QDL_CLK_VDO_AXI			167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX6QDL_CLK_VPU_AXI			168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX6QDL_CLK_CKO1			169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX6QDL_CLK_PLL1_SYS			170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX6QDL_CLK_PLL2_BUS			171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX6QDL_CLK_PLL3_USB_OTG		172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX6QDL_CLK_PLL4_AUDIO			173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX6QDL_CLK_PLL5_VIDEO			174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX6QDL_CLK_PLL8_MLB			175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX6QDL_CLK_PLL7_USB_HOST		176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX6QDL_CLK_PLL6_ENET			177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX6QDL_CLK_SSI1_IPG			178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX6QDL_CLK_SSI2_IPG			179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX6QDL_CLK_SSI3_IPG			180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX6QDL_CLK_ROM				181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX6QDL_CLK_USBPHY1			182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX6QDL_CLK_USBPHY2			183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX6QDL_CLK_LDB_DI0_DIV_3_5		184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX6QDL_CLK_LDB_DI1_DIV_3_5		185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX6QDL_CLK_SATA_REF			186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX6QDL_CLK_SATA_REF_100M		187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX6QDL_CLK_PCIE_REF			188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX6QDL_CLK_PCIE_REF_125M		189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX6QDL_CLK_ENET_REF			190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX6QDL_CLK_USBPHY1_GATE		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX6QDL_CLK_USBPHY2_GATE		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX6QDL_CLK_PLL4_POST_DIV		193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX6QDL_CLK_PLL5_POST_DIV		194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX6QDL_CLK_PLL5_VIDEO_DIV		195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX6QDL_CLK_EIM_SLOW			196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX6QDL_CLK_SPDIF			197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX6QDL_CLK_CKO2_SEL			198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX6QDL_CLK_CKO2_PODF			199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX6QDL_CLK_CKO2			200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX6QDL_CLK_CKO				201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX6QDL_CLK_VDOA			202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX6QDL_CLK_PLL4_AUDIO_DIV		203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX6QDL_CLK_LVDS1_SEL			204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IMX6QDL_CLK_LVDS2_SEL			205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX6QDL_CLK_LVDS1_GATE			206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMX6QDL_CLK_LVDS2_GATE			207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX6QDL_CLK_ESAI_IPG			208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IMX6QDL_CLK_ESAI_MEM			209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX6QDL_CLK_ASRC_IPG			210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IMX6QDL_CLK_ASRC_MEM			211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX6QDL_CLK_LVDS1_IN			212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IMX6QDL_CLK_LVDS2_IN			213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX6QDL_CLK_ANACLK1			214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMX6QDL_CLK_ANACLK2			215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX6QDL_PLL1_BYPASS_SRC			216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IMX6QDL_PLL2_BYPASS_SRC			217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX6QDL_PLL3_BYPASS_SRC			218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMX6QDL_PLL4_BYPASS_SRC			219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX6QDL_PLL5_BYPASS_SRC			220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMX6QDL_PLL6_BYPASS_SRC			221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX6QDL_PLL7_BYPASS_SRC			222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMX6QDL_CLK_PLL1			223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX6QDL_CLK_PLL2			224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMX6QDL_CLK_PLL3			225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMX6QDL_CLK_PLL4			226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMX6QDL_CLK_PLL5			227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX6QDL_CLK_PLL6			228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IMX6QDL_CLK_PLL7			229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX6QDL_PLL1_BYPASS			230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IMX6QDL_PLL2_BYPASS			231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX6QDL_PLL3_BYPASS			232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IMX6QDL_PLL4_BYPASS			233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMX6QDL_PLL5_BYPASS			234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMX6QDL_PLL6_BYPASS			235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX6QDL_PLL7_BYPASS			236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IMX6QDL_CLK_GPT_3M			237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX6QDL_CLK_VIDEO_27M			238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IMX6QDL_CLK_MIPI_CORE_CFG		239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IMX6QDL_CLK_MIPI_IPG			240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IMX6QDL_CLK_CAAM_MEM			241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX6QDL_CLK_CAAM_ACLK			242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMX6QDL_CLK_CAAM_IPG			243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX6QDL_CLK_SPDIF_GCLK			244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IMX6QDL_CLK_UART_SEL			245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX6QDL_CLK_IPG_PER_SEL			246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IMX6QDL_CLK_ECSPI_SEL			247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX6QDL_CLK_CAN_SEL			248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IMX6QDL_CLK_MMDC_CH1_AXI_CG		249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX6QDL_CLK_PRE0			250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IMX6QDL_CLK_PRE1			251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IMX6QDL_CLK_PRE2			252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IMX6QDL_CLK_PRE3			253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IMX6QDL_CLK_PRG0_AXI			254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IMX6QDL_CLK_PRG1_AXI			255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMX6QDL_CLK_PRG0_APB			256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IMX6QDL_CLK_PRG1_APB			257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX6QDL_CLK_PRE_AXI			258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMX6QDL_CLK_MLB_SEL			259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX6QDL_CLK_MLB_PODF			260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMX6QDL_CLK_EPIT1			261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IMX6QDL_CLK_EPIT2			262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IMX6QDL_CLK_MMDC_P0_IPG			263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IMX6QDL_CLK_DCIC1			264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IMX6QDL_CLK_DCIC2			265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IMX6QDL_CLK_END				266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */