^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DT_BINDINGS_CLOCK_IMX5_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DT_BINDINGS_CLOCK_IMX5_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define IMX5_CLK_DUMMY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IMX5_CLK_CKIL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX5_CLK_OSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX5_CLK_CKIH1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX5_CLK_CKIH2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX5_CLK_AHB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX5_CLK_IPG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX5_CLK_AXI_A 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX5_CLK_AXI_B 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX5_CLK_UART_PRED 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX5_CLK_UART_ROOT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX5_CLK_ESDHC_A_PRED 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX5_CLK_ESDHC_B_PRED 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX5_CLK_ESDHC_C_SEL 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX5_CLK_ESDHC_D_SEL 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX5_CLK_EMI_SEL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX5_CLK_EMI_SLOW_PODF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX5_CLK_NFC_PODF 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX5_CLK_ECSPI_PRED 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX5_CLK_ECSPI_PODF 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX5_CLK_USBOH3_PRED 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX5_CLK_USBOH3_PODF 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX5_CLK_USB_PHY_PRED 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX5_CLK_USB_PHY_PODF 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX5_CLK_CPU_PODF 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX5_CLK_DI_PRED 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX5_CLK_TVE_SEL 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX5_CLK_UART1_IPG_GATE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX5_CLK_UART1_PER_GATE 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX5_CLK_UART2_IPG_GATE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX5_CLK_UART2_PER_GATE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX5_CLK_UART3_IPG_GATE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX5_CLK_UART3_PER_GATE 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX5_CLK_I2C1_GATE 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX5_CLK_I2C2_GATE 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX5_CLK_GPT_IPG_GATE 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX5_CLK_PWM1_IPG_GATE 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX5_CLK_PWM1_HF_GATE 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX5_CLK_PWM2_IPG_GATE 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX5_CLK_PWM2_HF_GATE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX5_CLK_GPT_HF_GATE 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX5_CLK_FEC_GATE 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX5_CLK_USBOH3_PER_GATE 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX5_CLK_ESDHC1_IPG_GATE 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX5_CLK_ESDHC2_IPG_GATE 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX5_CLK_ESDHC3_IPG_GATE 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX5_CLK_ESDHC4_IPG_GATE 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX5_CLK_SSI1_IPG_GATE 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX5_CLK_SSI2_IPG_GATE 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX5_CLK_SSI3_IPG_GATE 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX5_CLK_ECSPI1_IPG_GATE 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX5_CLK_ECSPI1_PER_GATE 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX5_CLK_ECSPI2_IPG_GATE 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX5_CLK_ECSPI2_PER_GATE 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX5_CLK_CSPI_IPG_GATE 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX5_CLK_SDMA_GATE 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX5_CLK_EMI_SLOW_GATE 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX5_CLK_IPU_SEL 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX5_CLK_IPU_GATE 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX5_CLK_NFC_GATE 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX5_CLK_IPU_DI1_GATE 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX5_CLK_VPU_SEL 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX5_CLK_VPU_GATE 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX5_CLK_VPU_REFERENCE_GATE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX5_CLK_UART4_IPG_GATE 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX5_CLK_UART4_PER_GATE 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX5_CLK_UART5_IPG_GATE 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX5_CLK_UART5_PER_GATE 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX5_CLK_TVE_GATE 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX5_CLK_TVE_PRED 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX5_CLK_ESDHC1_PER_GATE 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX5_CLK_ESDHC2_PER_GATE 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX5_CLK_ESDHC3_PER_GATE 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX5_CLK_ESDHC4_PER_GATE 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX5_CLK_USB_PHY_GATE 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX5_CLK_HSI2C_GATE 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX5_CLK_MIPI_HSC1_GATE 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX5_CLK_MIPI_HSC2_GATE 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX5_CLK_MIPI_ESC_GATE 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX5_CLK_MIPI_HSP_GATE 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX5_CLK_LDB_DI1_DIV_3_5 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX5_CLK_LDB_DI1_DIV 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX5_CLK_LDB_DI0_DIV_3_5 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX5_CLK_LDB_DI0_DIV 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX5_CLK_LDB_DI1_GATE 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX5_CLK_CAN2_SERIAL_GATE 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX5_CLK_CAN2_IPG_GATE 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX5_CLK_I2C3_GATE 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX5_CLK_LP_APM 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX5_CLK_PERIPH_APM 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX5_CLK_MAIN_BUS 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX5_CLK_AHB_MAX 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX5_CLK_AIPS_TZ1 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX5_CLK_AIPS_TZ2 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX5_CLK_TMAX1 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX5_CLK_TMAX2 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX5_CLK_TMAX3 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX5_CLK_SPBA 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX5_CLK_UART_SEL 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX5_CLK_ESDHC_A_SEL 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX5_CLK_ESDHC_B_SEL 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX5_CLK_ESDHC_A_PODF 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX5_CLK_ESDHC_B_PODF 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX5_CLK_ECSPI_SEL 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX5_CLK_USBOH3_SEL 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX5_CLK_USB_PHY_SEL 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX5_CLK_IIM_GATE 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX5_CLK_USBOH3_GATE 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX5_CLK_EMI_FAST_GATE 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX5_CLK_IPU_DI0_GATE 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX5_CLK_GPC_DVFS 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX5_CLK_PLL1_SW 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX5_CLK_PLL2_SW 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX5_CLK_PLL3_SW 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX5_CLK_IPU_DI0_SEL 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX5_CLK_IPU_DI1_SEL 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX5_CLK_TVE_EXT_SEL 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX5_CLK_MX51_MIPI 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX5_CLK_PLL4_SW 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX5_CLK_LDB_DI1_SEL 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX5_CLK_DI_PLL4_PODF 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX5_CLK_LDB_DI0_SEL 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX5_CLK_LDB_DI0_GATE 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX5_CLK_USB_PHY1_GATE 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX5_CLK_USB_PHY2_GATE 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX5_CLK_PER_LP_APM 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX5_CLK_PER_PRED1 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX5_CLK_PER_PRED2 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX5_CLK_PER_PODF 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX5_CLK_PER_ROOT 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX5_CLK_SSI_APM 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX5_CLK_SSI1_ROOT_SEL 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX5_CLK_SSI2_ROOT_SEL 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX5_CLK_SSI3_ROOT_SEL 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX5_CLK_SSI_EXT1_SEL 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX5_CLK_SSI_EXT2_SEL 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX5_CLK_SSI_EXT1_COM_SEL 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX5_CLK_SSI_EXT2_COM_SEL 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX5_CLK_SSI1_ROOT_PRED 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX5_CLK_SSI1_ROOT_PODF 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX5_CLK_SSI2_ROOT_PRED 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX5_CLK_SSI2_ROOT_PODF 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX5_CLK_SSI_EXT1_PRED 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX5_CLK_SSI_EXT1_PODF 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX5_CLK_SSI_EXT2_PRED 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX5_CLK_SSI_EXT2_PODF 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX5_CLK_SSI1_ROOT_GATE 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX5_CLK_SSI2_ROOT_GATE 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX5_CLK_SSI3_ROOT_GATE 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX5_CLK_SSI_EXT1_GATE 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX5_CLK_SSI_EXT2_GATE 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX5_CLK_EPIT1_IPG_GATE 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX5_CLK_EPIT1_HF_GATE 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX5_CLK_EPIT2_IPG_GATE 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX5_CLK_EPIT2_HF_GATE 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX5_CLK_CAN_SEL 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX5_CLK_CAN1_SERIAL_GATE 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX5_CLK_CAN1_IPG_GATE 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX5_CLK_OWIRE_GATE 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX5_CLK_GPU3D_SEL 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX5_CLK_GPU2D_SEL 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX5_CLK_GPU3D_GATE 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX5_CLK_GPU2D_GATE 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX5_CLK_GARB_GATE 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX5_CLK_CKO1_SEL 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX5_CLK_CKO1_PODF 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX5_CLK_CKO1 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX5_CLK_CKO2_SEL 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX5_CLK_CKO2_PODF 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX5_CLK_CKO2 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX5_CLK_SRTC_GATE 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX5_CLK_PATA_GATE 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX5_CLK_SATA_GATE 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX5_CLK_SPDIF_XTAL_SEL 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX5_CLK_SPDIF0_SEL 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX5_CLK_SPDIF1_SEL 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX5_CLK_SPDIF0_PRED 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX5_CLK_SPDIF0_PODF 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX5_CLK_SPDIF1_PRED 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX5_CLK_SPDIF1_PODF 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX5_CLK_SPDIF0_COM_SEL 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX5_CLK_SPDIF1_COM_SEL 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX5_CLK_SPDIF0_GATE 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX5_CLK_SPDIF1_GATE 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX5_CLK_SPDIF_IPG_GATE 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX5_CLK_OCRAM 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX5_CLK_SAHARA_IPG_GATE 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX5_CLK_SATA_REF 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX5_CLK_STEP_SEL 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX5_CLK_CPU_PODF_SEL 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX5_CLK_ARM 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX5_CLK_FIRI_PRED 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX5_CLK_FIRI_SEL 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX5_CLK_FIRI_PODF 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX5_CLK_FIRI_SERIAL_GATE 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX5_CLK_FIRI_IPG_GATE 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX5_CLK_CSI0_MCLK1_PRED 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX5_CLK_CSI0_MCLK1_SEL 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX5_CLK_CSI0_MCLK1_PODF 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX5_CLK_CSI0_MCLK1_GATE 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX5_CLK_IEEE1588_PRED 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX5_CLK_IEEE1588_SEL 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX5_CLK_IEEE1588_PODF 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX5_CLK_IEEE1588_GATE 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX5_CLK_SCC2_IPG_GATE 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX5_CLK_END 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #endif /* __DT_BINDINGS_CLOCK_IMX5_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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