Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_CLOCK_IMX21_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_CLOCK_IMX21_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define IMX21_CLK_DUMMY			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IMX21_CLK_CKIL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX21_CLK_CKIH			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX21_CLK_FPM			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX21_CLK_CKIH_DIV1P5		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX21_CLK_MPLL_GATE		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX21_CLK_SPLL_GATE		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX21_CLK_FPM_GATE		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX21_CLK_CKIH_GATE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX21_CLK_MPLL_OSC_SEL		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX21_CLK_IPG			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX21_CLK_HCLK			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX21_CLK_MPLL_SEL		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX21_CLK_SPLL_SEL		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX21_CLK_SSI1_SEL		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX21_CLK_SSI2_SEL		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX21_CLK_USB_DIV		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX21_CLK_FCLK			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX21_CLK_MPLL			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX21_CLK_SPLL			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX21_CLK_NFC_DIV		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX21_CLK_SSI1_DIV		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX21_CLK_SSI2_DIV		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX21_CLK_PER1			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX21_CLK_PER2			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX21_CLK_PER3			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX21_CLK_PER4			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX21_CLK_UART1_IPG_GATE	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX21_CLK_UART2_IPG_GATE	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX21_CLK_UART3_IPG_GATE	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX21_CLK_UART4_IPG_GATE	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX21_CLK_CSPI1_IPG_GATE	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX21_CLK_CSPI2_IPG_GATE	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX21_CLK_SSI1_GATE		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX21_CLK_SSI2_GATE		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX21_CLK_SDHC1_IPG_GATE	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX21_CLK_SDHC2_IPG_GATE	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX21_CLK_GPIO_GATE		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX21_CLK_I2C_GATE		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX21_CLK_DMA_GATE		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX21_CLK_USB_GATE		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX21_CLK_EMMA_GATE		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX21_CLK_SSI2_BAUD_GATE	42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX21_CLK_SSI1_BAUD_GATE	43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX21_CLK_LCDC_IPG_GATE		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX21_CLK_NFC_GATE		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX21_CLK_LCDC_HCLK_GATE	46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX21_CLK_PER4_GATE		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX21_CLK_BMI_GATE		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX21_CLK_USB_HCLK_GATE		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX21_CLK_SLCDC_GATE		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX21_CLK_SLCDC_HCLK_GATE	51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX21_CLK_EMMA_HCLK_GATE	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX21_CLK_BROM_GATE		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX21_CLK_DMA_HCLK_GATE		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX21_CLK_CSI_HCLK_GATE		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX21_CLK_CSPI3_IPG_GATE	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX21_CLK_WDOG_GATE		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX21_CLK_GPT1_IPG_GATE		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX21_CLK_GPT2_IPG_GATE		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX21_CLK_GPT3_IPG_GATE		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX21_CLK_PWM_IPG_GATE		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX21_CLK_RTC_GATE		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX21_CLK_KPP_GATE		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX21_CLK_OWIRE_GATE		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX21_CLK_MAX			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif