Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_CLOCK_IMX1_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_CLOCK_IMX1_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define IMX1_CLK_DUMMY		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IMX1_CLK_CLK32		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX1_CLK_CLK16M_EXT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX1_CLK_CLK16M		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX1_CLK_CLK32_PREMULT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX1_CLK_PREM		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX1_CLK_MPLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX1_CLK_MPLL_GATE	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX1_CLK_SPLL		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX1_CLK_SPLL_GATE	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX1_CLK_MCU		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX1_CLK_FCLK		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX1_CLK_HCLK		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX1_CLK_CLK48M		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX1_CLK_PER1		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX1_CLK_PER2		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX1_CLK_PER3		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX1_CLK_CLKO		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX1_CLK_UART3_GATE	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX1_CLK_SSI2_GATE	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX1_CLK_BROM_GATE	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX1_CLK_DMA_GATE	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX1_CLK_CSI_GATE	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX1_CLK_MMA_GATE	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX1_CLK_USBD_GATE	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX1_CLK_MAX		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif