Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (c) 2014 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __DTS_HIX5HD2_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __DTS_HIX5HD2_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* fixed rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define HIX5HD2_FIXED_1200M		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define HIX5HD2_FIXED_400M		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define HIX5HD2_FIXED_48M		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HIX5HD2_FIXED_24M		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define HIX5HD2_FIXED_600M		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HIX5HD2_FIXED_300M		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HIX5HD2_FIXED_75M		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HIX5HD2_FIXED_200M		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HIX5HD2_FIXED_100M		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HIX5HD2_FIXED_40M		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HIX5HD2_FIXED_150M		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HIX5HD2_FIXED_1728M		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HIX5HD2_FIXED_28P8M		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HIX5HD2_FIXED_432M		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HIX5HD2_FIXED_345P6M		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HIX5HD2_FIXED_288M		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HIX5HD2_FIXED_60M		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HIX5HD2_FIXED_750M		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HIX5HD2_FIXED_500M		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HIX5HD2_FIXED_54M		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HIX5HD2_FIXED_27M		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HIX5HD2_FIXED_1500M		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HIX5HD2_FIXED_375M		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HIX5HD2_FIXED_187M		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HIX5HD2_FIXED_250M		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HIX5HD2_FIXED_125M		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HIX5HD2_FIXED_2P02M		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HIX5HD2_FIXED_50M		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HIX5HD2_FIXED_25M		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HIX5HD2_FIXED_83M		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* mux clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HIX5HD2_SFC_MUX			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HIX5HD2_MMC_MUX			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HIX5HD2_FEPHY_MUX		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HIX5HD2_SD_MUX			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HIX5HD2_SFC_RST			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HIX5HD2_SFC_CLK			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HIX5HD2_MMC_CIU_CLK		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HIX5HD2_MMC_BIU_CLK		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HIX5HD2_MMC_CIU_RST		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HIX5HD2_FWD_BUS_CLK		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HIX5HD2_FWD_SYS_CLK		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HIX5HD2_MAC0_PHY_CLK		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HIX5HD2_SD_CIU_CLK		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HIX5HD2_SD_BIU_CLK		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HIX5HD2_SD_CIU_RST		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HIX5HD2_WDG0_CLK		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HIX5HD2_WDG0_RST		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HIX5HD2_I2C0_CLK		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HIX5HD2_I2C0_RST		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HIX5HD2_I2C1_CLK		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HIX5HD2_I2C1_RST		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HIX5HD2_I2C2_CLK		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HIX5HD2_I2C2_RST		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HIX5HD2_I2C3_CLK		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HIX5HD2_I2C3_RST		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HIX5HD2_I2C4_CLK		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HIX5HD2_I2C4_RST		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HIX5HD2_I2C5_CLK		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HIX5HD2_I2C5_RST		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* complex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HIX5HD2_MAC0_CLK		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HIX5HD2_MAC1_CLK		193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HIX5HD2_SATA_CLK		194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HIX5HD2_USB_CLK			195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HIX5HD2_NR_CLKS			256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif	/* __DTS_HIX5HD2_CLOCK_H */